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d a t a sh eet objective speci?cation file under integrated circuits, ic01 1997 aug 01 integrated circuits SAA7391 atapi cd-r block encoder/decoder
1997 aug 01 2 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 contents 1 features 2 general description 2.1 memory mapped control registers 2.2 error correction features 2.3 host interface features 2.4 buffer memory organisation 2.5 subcode handling features 2.6 multimedia output audio control features 3 quick reference data 4 ordering information 5 block diagram 6 pinning 6.1 detailed description of pin functions 7 functional description 7.1 memory field description 7.1.1 dvd-rom memory field information 7.2 cd input control registers 7.2.1 registers associated with data in process 7.3 multimedia output interface 7.3.1 subcode input block 7.3.2 subcode mode transmit control register 7.3.3 general description of the multimedia output interface 7.3.4 iec 958/ebu output 7.3.5 memory-to-memory block copy function 7.4 interrupt registers 7.4.1 interrupt 1 7.4.2 interrupt 2 7.4.3 uart interrupt 7.5 host interface 7.5.1 introduction 7.5.2 description of the host interface block 7.5.3 description of the host interface registers 7.5.4 transfer counter 7.5.5 packet size store 7.5.6 sequencer status 7.5.7 host interface dma special bits 7.5.8 automatic block pointer reload programming 7.5.9 dma transfer programming of the host interface 7.5.10 generic interface operation 7.5.11 dma transfers in generic mode 7.5.12 normal dma mode 7.5.13 burst dma mode using multiplexed bus configuration 7.6 microcontroller interface 7.6.1 kernel based firmware 7.6.2 16-bit registers automatic read and write 7.7 8051 cpu and memory management functions 7.7.1 sub-cpu bus access timing 7.7.2 buffer memory organisation 7.7.3 subpage 7.8 external memory interface 7.8.1 dram interface configuration register 7.9 uart for communication with cd engine 7.9.1 uart basic engine interface 7.10 clock generation control 7.10.1 crystal oscillator 7.10.2 sub-cpu clock control register 7.10.3 SAA7391 system clock control registers 8 limiting values 9 thermal characteristics 10 characteristics 11 timing characteristics 11.1 external memory interface timing 11.2 host interface timing 11.2.1 host interface atapi pio and dma timing 11.2.2 ata bus timing 11.2.3 ultra dma operation and timing 11.2.4 ultra dma read/write timing 11.3 sub-cpu interface timing 11.4 uart timing 12 appendix a 13 application information 14 package outline 15 soldering 15.1 introduction 15.2 reflow soldering 15.3 wave soldering 15.4 repairing soldered joints 16 definitions 17 life support applications
1997 aug 01 3 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 1 features supports real time error detection and correction in hardware. error correction to n = 27, error detect to n = 30 and raw data transfer to n = 32. cd-r to cd-n greater than 8. internal operation is faster, but firmware and physical (laser/media) factors limit the speed dvd-rom supported in combination with the saa7335 direct generic interface to external small computer systems interface (scsi) controller devices operates with up to 16 mbytes dram C hyper-page dram up to 33 mbytes words/s burst C fast-page dram at up to 17.5 mbytes words/s burst has fixed n = 1 or n = 2 rate (44.1 or 88.2 khz) i 2 s-bus multimedia output for simple audio/video output; features for cav/quasi-clv support C supports philips multimedia audio codec C provides shoarma red book audio buffer iec 958 (spdif, aes/ebu and dobm) output with q-w subcode and programmable category code, output at n = 1 rate device registers are memory mapped for faster direct access to the chip provides direct access from sub-cpu to buffer ram to support scratchpad accesses. this eliminates the need for extra ram chips in the system automatic sequencing of atapi packet command protocol, including command termination automated data transfers to and from the host using pio, dma and ultra dma. 2 general description the SAA7391 is a block decoder/encoder and buffer manager for high-speed cd-rom/cd-r functions, that integrates real time error correction and detection and bidirectional atapi transfer functions into a single chip. 2.1 memory mapped control registers the SAA7391 device has a large number of memory mapped registers. these are arranged so that high-level languages see the registers as external byte or 16-bit integer quantities. the block addressing of the SAA7391 facilitates the use of pairs of 16-bit quantities to represent addresses. the reading and writing of 16-bit registers within the device can be performed by two separate 8-bit reads, where the second byte data is latched at the same time as the first byte is read. 2.2 error correction features the SAA7391 has an on-chip 36 kbits memory that is used as a buffer memory for error and erasure correction processing. this buffer memory reduces the number of external ram accesses that are needed for error correction and thus allows for an increased rate of data throughput. the error corrector is switchable between two-pass, single-pass [both with error detection/correction (edc)] and edc only modes to further improve throughput. the presence of the full error corrector removes the need for firmware based control of the error correctors operation. 2.3 host interface features the SAA7391 has an atapi host interface that may be directly connected to the atapi bus thereby reducing the need for external support devices. it supports pio mode 4 transfer and mode 0 ultra dma. this interface can also be configured as a generic dma interface for use with external host interface devices (e.g. scsi controller). the dma interface has the following features: atapi command packets are automatically loaded into the command fifo data transfer to the host is automatically sequenced to reduce inter-block latencies and improve host cpu utilisation host data transfer rate is independent of error corrector operation and the data input path the host interface features automatic determination of block length for mode 2, form 1 and form 2 sectors. the block length transferred is programmable. the host interface can transfer up to 3 sub-blocks per sector, with each sub-block being transferred dependent on the form bit. automatic reload of sub-block pointers and unconditional transfer are supported.
1997 aug 01 4 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 2.4 buffer memory organisation memory is mapped as a 16-bit block number and 12-bit offset into that block. the block oriented memory structure permits the use of 16-bit pointers in software thereby minimising the overhead of accessing memory. the address can be found from the following equation: address = block number 2560 + offset. the microcontroller sees the SAA7391 as a memory mapped peripheral, with control and status registers appearing in the upper address space. the lowest 52 kbytes (48 kbyte s + 4 kbytes) of the 8051 microcontroller external address space is mapped as a window into the memory on a user-specified 1 kbyte boundary within the buffer ram. this can be used as a scratchpad memory. the next 4 kbytes is separately mapped as a window into the memory on a user-specified 1 kbyte boundary within the ram. the next 7.5 kbytes of the external data space consists of three independently addressed memory segments for accessing block data, subcode information and block headers. the registers of the SAA7391 are mapped into the top 256 bytes of external data space. 2.5 subcode handling features the writing of data into the buffer ram is aligned to the absolute time sync marker with the following features: subcodes are written into memory together with their associated sector data.this eases the provision of specialist features, for example cd + g or karaoke cd applications. all channels of subcode are de-interleaved the q channel is also cyclic redundancy checked (crc) for increased reliability when operating in 3-wire subcode mode, it is possible to control or read the p bit in the p-w subcode stream. 2.6 multimedia output audio control features the i 2 s-bus input may be processed before feeding to the multimedia audio output in several simple ways: as audio is transferred via the buffer memory, it is not necessary to have the cd-dsp i 2 s-bus input at exactly the audio n = 1 or video n = 2 rate. any faster speed will work because the buffer ram is used as a fifo. both channels may be independently controlled. the left channel output may be sourced from zero (digital silence), left or right input; this also applies for the right channel output. this permits basic audio switching and channel swapping. iec 958 (spdif, aes/ebu and dobm) output with q-w subcode and programmable category code, can be output from the same cd-dsp i 2 s-bus data source. 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v ddd(core) digital core supply voltage 3.0 3.3 3.6 v v ddd(pad) digital peripheral supply voltage v ddd(core) 5.0 or 3.3 5.0 v i ddd supply current tbf 60 tbf ma f xtal crystal frequency 8 8.4672, 16.9344 or 33.8688 35 mhz t amb operating ambient temperature 0 - 70 c t stg storage temperature - 55 - +125 c type number package name description version SAA7391h lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1
1997 aug 01 5 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 5 block diagram fig.1 the SAA7391 internal block diagram. handbook, full pagewidth mgk506 atapi host interface system clock generator multimedia interface test control block subcode interface sub-cpu interface drive interface error corrector encoder external dram memory processor SAA7391 ide-bus sub-cpu clock master clock iec 958 subcode from cd-dsp subcode to cd-r i 2 s-bus from cd-dsp i 2 s-bus to cd-r i 2 s-bus to dac
1997 aug 01 6 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 6 pinning symbol pin type drive/ threshold grouping description n.c. 1 -- - not connected n.c. 2 -- - not connected xda0 3 o m ram output address lines xda1 4 o m xda2 5 o m v ddd(pad6) 6 -- - digital peripheral supply voltage 6 dgnd1 7 -- - digital ground 1 xda3 8 o m ram output address lines xda4 9 o m xda5 10 o m xda6 11 o m xda7 12 o m xda8 13 o m xda9 14 o m xda10 15 o m xda11 16 o m dgnd2 17 -- - digital ground 2 xras 18 o h ram row address strobe output (active low) xcas 19 o h column address strobe output (active low) xwr 20 o h write enable output (active low) xdd0 21 i/o m/t ram data bus input/output xdd1 22 i/o m/t v ddd(core1) 23 -- - digital core supply voltage 1 dgnd3 24 -- - digital ground 3 xdd2 25 i/o m/t ram data bus input/output xdd3 26 i/o m/t xdd4 27 i/o m/t xdd5 28 i/o m/t xdd6 29 i/o m/t xdd7 30 i/o m/t v ddd(pad7) 31 -- - digital peripheral supply voltage 7 dgnd4 32 -- - digital ground 4 scki1 33 i c i 2 s-bus i/o i 2 s-bus bit clock input wsi1 34 i c i 2 s-bus word select strobe input
1997 aug 01 7 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 n.c. 35 to 38 -- - not connected sdi1 39 i c i 2 s-bus i/o data input from cd engine sdo1 40 o m data output to cd-r writer sfsy 41 i/o l/c subcode i/o 3-wire subcode sync input/output rck 42 i/o l/c 3-wire subcode clock input/output subi 43 i c q and r-w subcode input subo 44 o l subcode output from encoder to writer cflg 45 i c i 2 s-bus input cd error corrector ?ags and absolute time sync c2p0 46 i c cd c2 error correction ?ag input for erco dgnd5 47 -- - digital ground 5 ieco 48 o m multimedia iec 958 output mck 49 i/o m/c multimedia output 256f s or 384f s clock for multimedia master clock/iec 958 clock or divided system clock for cd-dsp sck2 50 i/o l/c multimedia i 2 s-bus bit clock input/output ws2 51 i/o l/c i 2 s-bus word select strobe input/output sdo2 52 o m i 2 s-bus data output to dac/video decoder gnd 53 -- - ground crout 54 o crystal pad crystal oscillator crystal oscillator output crin 55 i crystal pad crystal oscillator/clock input v dda 56 -- - analog supply voltage i ref 57 analog current input clock generator vco reference current por 58 i schmitt trigger system power-on reset (active low) test1 59 i c test mode control input test pins test2 60 i c reset 61 i schmitt trigger host atapi bus reset input from host (active low) dd7 62 i/o al/t host data bus input/output dd8 63 i/o al/t dd6 64 i/o al/t v ddd(pad1) 65 -- - digital peripheral supply voltage 1 dgnd6 66 -- - digital ground 6 dd9 67 i/o al/t host data bus pin order of atapi interface matches the pinning of the 40-way ide connector (slew rate limiting by control of drive capability into capacitive load of ata bus) dd5 68 i/o al/t dd10 69 i/o al/t dd4 70 i/o al/t symbol pin type drive/ threshold grouping description
1997 aug 01 8 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 n.c. 71 to 74 -- - not connected dd11 75 i/o al/t host data bus; pin order of atapi interface matches the pinning of the 40-way ide connector (slew rate limiting by control of drive capability into capacitive load of ata bus) dd3 76 i/o al/t dd12 77 i/o al/t dd2 78 i/o al/t dd13 79 i/o al/t dd1 80 i/o al/t dd14 81 i/o al/t dd0 82 i/o al/t dd15 83 i/o al/t dmarq/ dmack 84 o al host dma request/scsi dma acknowledge output (active low) dgnd7 85 -- - digital ground 7 v ddd(pad2) 86 -- - digital peripheral supply voltage 2 diow 87 i l/t host write cycle write enable/control register write input (active low) dior 88 i l/t host read cycle read enable/control register read input (active low) iordy 89 o ah host device is ready to transfer data output (active low) dmack/ dmarq 90 i t host dma acknowledge (active low)/scsi dma request input intrq 91 a host host interrupt request (nb 3-state output) dgnd8 92 -- - digital ground 8 v ddd(pad3) 93 -- - digital peripheral supply voltage 3 iocs16 94 o ah host i/o port is 16-bit output (active low) da1/ dbwr 95 i/o l/t host address wire 1/dma from generic interface is output from the SAA7391 (active low) pdiag 96 i/o al/t host atapi passed diagnostics input/output (active low) da0 97 i/o l/t host address wire 0 input/output da2/ dbrd 98 i/o l/t host address wire 2/dma from generic interface is input to the SAA7391 (active low) cs0/ scsics 99 i/o l/t host chip select 1fx/generic interface chip select (active low) cs1 100 i/o l/t host chip select 3fx input/output (active low) dasp 101 i/o ah/t host device active slave present input/output (active low) int2 102 o l sub-cpu sub-cpu interrupt output from the SAA7391 drive block and uart symbol pin type drive/ threshold grouping description
1997 aug 01 9 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 dgnd9 103 -- - digital ground 9 v ddd(pad4) 104 -- - digital peripheral supply voltage 4 comack 105 i c uart command acknowledge/transmit ?ow control input comclk 106 o l uart serial data clock for synchronous mode output n.c. 107 to 110 -- - not connected comout 111 o l uart transmit data output comin 112 i c uart receive data input comsync 113 i c uart basic engine synchronization input syssync 114 i c uart basic engine synchronization input scclk 115 o m sub-cpu sub-cpu clock output rd 116 i t sub-cpu sub-cpu read enable (active low) wr/r/ w 117 i t sub-cpu sub-cpu write enable/and read/write control input (active low) int 118 o l sub-cpu sub-cpu interrupt request output from host interface (active low) srst 119 o l sub-cpu sub-cpu reset output sca0/scd0 120 i/o l/t sub-cpu multiplexed address/data lines sca1/scd1 121 i/o l/t dgnd10 122 -- - digital ground 10 v ddd(pad5) 123 -- - digital peripheral supply voltage 6 sca2/scd2 124 i/o l/t sub-cpu multiplexed address/data lines sca3/scd3 125 i/o l/t sca4/scd4 126 i/o l/t sca5/scd5 127 i/o l/t sca6/scd6 128 i/o l/t sca7/scd7 129 i/o l/t dgnd11 130 -- - digital ground 11 v ddd(core2) 131 -- - digital core supply voltage 2 ale 132 i t sub-cpu demultiplex enable input for lower address lines psen 133 i t sub-cpu program store enable (active low) sca15 134 i t sub-cpu upper address lines input sca14 135 i t sca13 136 i t sca12 137 i t dgnd12 138 -- - digital ground 12 symbol pin type drive/ threshold grouping description
1997 aug 01 10 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 sca11 139 i t sub-cpu upper address lines input sca10 140 i t sca9 141 i t sca8 142 i t n.c. 143 -- - not connected n.c. 144 -- - not connected symbol pin type drive/ threshold grouping description
1997 aug 01 11 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.2 pin configuration. handbook, full pagewidth mgk542 SAA7391 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 n.c. n.c. xda0 xda1 xda2 v ddd(pad6) dgnd1 xda3 xda4 xda5 xda6 xda7 xda8 xda9 xda10 xda11 dgnd2 xwr xdd0 xdd1 v ddd(core1) dgnd3 xdd2 xdd3 xdd4 xdd5 xdd6 xdd7 v ddd(pad7) dgnd4 scki1 wsi1 n.c. n.c. n.c. n.c. comclk comack v ddd(pad4) dgnd9 int2 dasp cs1 cs0/scics da2/dbrd da0 pdiag da1/dbwr iocs16 v ddd(pad3) dgnd8 intrq dmack/dmarq iordy dior diow v ddd(pad2) dgnd7 dmarq/dmack dd15 dd0 dd14 dd1 dd13 dd2 dd12 dd3 dd11 n.c n.c. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 n.c. n.c. sdi1 sdo1 sfsy rck subi subo cflg c2p0 dgnd5 ieco mck sck2 ws2 sdo2 gnd crout crin v dda i ref test1 test2 dd7 dd8 dd6 v ddd(pad1) dgnd6 dd9 dd5 dd10 dd4 n.c. n.c. n.c. n.c. sca8 sca9 sca10 sca11 dgnd12 sca12 sca13 sca14 sca15 psen ale v ddd(core2) dgnd11 sca7/scd7 sca6/scd6 sca5/scd5 sca4/scd4 sca3/scd3 sca2/scd2 v ddd(pad5) dgnd10 sca1/scd1 sca0/scd0 srst int wr/r/w rd scclk syssync comsync comin comout n.c. n.c. 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 xras xcas por reset
1997 aug 01 12 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 6.1 detailed description of pin functions table 1 q and r-w input/output subcode connections (4 pins) table 2 i 2 s-bus multimedia audio output (5 pins) table 3 i 2 s-bus connections to cd engine (6 pins) symbol description comment sfsy 3-wire subcode sync input subcode frame sync for receiving 3-wire subcode; output subcode frame sync for transmitting 3-wire subcode rck 3-wire subcode clock output bit clock for receiving 3-wire subcode; input bit clock for transmitting 3-wire subcode subi q and r-w subcode input con?gurable for 3-wire or philips v4 subcode mode; can use either rck or wsi1 as clock references with appropriate dividers subo output subcode from encode con?gurable for philips sri (subcode recordable interface) 3-wire or philips v4 subcode mode; can use either rck, wsi1 or ws2 as clock references symbol description comment mck 256f s or 384f s clock for multimedia master clock/iec 958 clock or divided system clock for cd-dsp clock reference input pin when interface is in a master mode; a programmable divider is provided. this pin is also con?gurable as a programmable clock output intended as a clock reference for a cd-dsp. should be pulled up if not in use. sck2 i 2 s-bus bit clock this is used for master and slave i 2 s-bus application as both modes are needed. for instance, the philips multimedia codec is an i 2 s-bus slave, hence this must be a master interface. when driving some dacs, this interface can be a slave. ws2 i 2 s-bus left/right strobe word select strobe either master or slave sdo2 i 2 s-bus data to dac/video decoder i 2 s-bus multimedia data ieco iec 958 output the iec 958 output combines multimedia data and q-w subcode symbol description comment scki1 i 2 s-bus bit clock this is a separate clock to the multimedia bit clock as this rate is derived from the disc linear velocity wsi1 i 2 s-bus left/right strobe sdi1 i 2 s-bus data from cd-dsp sdo1 i 2 s-bus data to cd-writer c2p0 cd c2 error corrector ?ag from erco these ?ags are used to indicate errors from second layer correction to the erco cflg cd error corrector ?ags and absolute time sync the absolute time sync is used in the cd input process for playing red book discs; the error corrector status is also read in from this signal, to provide an indication of c1 and c2 performance for cd-rw applications.
1997 aug 01 13 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 4 atapi target mode interface atapi name atapi meaning reset atapi reset signal: the SAA7391 will not recognize a signal assertion shorter than 20 ns as a valid reset signal. dd0 to dd7 atapi d0 to d7 dd8 to dd15 atapi d8 to d15: these data bits are only used in accesses to the 16-bit data port dmarq dma request: this signal, used for dma data transfers between host and device, is asserted by the SAA7391 when it is ready to transfer data to or from the host. the direction of data transfer is controlled by dior and diow. dmack dma acknowledge: this signal is used by the host in response to dmarq to initiate dma transfers. this signal may be temporarily negated by the host to suspend the dma transfer in process. iocs16 atapi i/o port is a 16-bit open-drain output: during pio transfer modes 0, 1 or 2, iocs16 indicates to the host system that the 16-bit data port has been addressed and that the device is prepared to send or receive a 16-bit data word. iordy atapi i/o ready open-drain output: this signal is negated to extend the host transfer cycle of any host register access (read or write) when the SAA7391 is not ready to respond to a data transfer request. this signal is only enabled during dior/diow cycles to the SAA7391. when iordy is not active, it is in the high-impedance (undriven) state. da0 to da2 address bus (device address) diow atapi write strobe: the rising edge of diow latches data from the signals, dd0 to dd7 or dd0 to dd15 into a register or the data port of the SAA7391. the SAA7391 will not act on the data until it is latched. dior atapi read strobe: the falling edge of dior enables data from a register or data port of the SAA7391 onto the signals, dd0 to dd7 or dd0 to dd15. the rising edge of dior latches data at the host and the host will not act on the data until it is latched. cs0 atapi chip select 0 input: this is the chip select signal from the host used to select the ata command block registers. this signal is also known as cs1fx. cs1 atapi chip select 1 input: this is the chip select signal from the host used to select the ata control block registers. this signal is also known as cs3fx. intrq atapi interrupt output: this signal is used to interrupt the host system. intrq is asserted only when the device has a pending interrupt, the device is selected, and the host has cleared the nien bit in the device control register. if the nien bit is equal to 1, or the device is not selected, this output is in a high-impedance state, regardless of the presence or absence of a pending interrupt. pdiag atapi passed diagnostics: this signal shall be asserted by device 1 to indicate to device 0 that it has completed diagnostics. dasp atapi dasp (device active, device 1 present): this is a time-multiplexed signal which indicates that a device is active, or that device 1 is present. this signal is an open-drain output.
1997 aug 01 14 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 5 generic host controller interface table 6 miscellaneous pins table 7 sub-cpu interface pins atapi name generic interface name generic host controller interface meaning reset reset controller reset output dd0 to dd7 d0 to d7 controller dma path/controller data and control bus (optional) dd8 to dd15 d8 to d15 controller upper dma path (optional) dmarq dmack dma acknowledge to controller dmack dmarq dma request from controller da1 dbwr dma bus write to controller da2 dbrd dma bus read from controller cs0 scsics controller chip select output for sub-cpu read/write cycles symbol description comment crin crystal oscillator/clock input - crout crystal oscillator output - i ref vco reference current clock pll multiplier por power-on reset pin - test1 and test2 mode control test pins - symbol description comment srst sub-cpu reset active high reset if xdd7 is pulled low during power-on reset; active low reset if xdd7 is pulled high during power-on reset int sub-cpu interrupt request output from host interface open-drain sub-processor interrupt from host interface int2 sub-cpu interrupt output from the SAA7391 drive block and uart open-drain sub-processor interrupt from drive and uart scclk sub-cpu clock out - rd sub-cpu read enable sub-cpu read enable strobe; if grounded permanently, the wr signal will act as read/write control input wr/r/ w sub-cpu write enable/ read/write control write enable; alternative usage is read/ write if rd is held low at all times; wr has priority over rd at all times ale demultiplex enable input for lower address lines while high, the lower address bits are latched from scd0 to scd7; should be used with a schmitt trigger input to avoid false latching due to ground bounce on the 8051 microcontroller
1997 aug 01 15 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 8 ram interface pins table 9 basic engine interface psen program store enable if this pin is low then the 8051 microcontroller is accessing external program store; this pin is used as an active high chip enable scd0 to scd7/ sca0 to sca7 sub-cpu data bus multiplexed/low address bus - sca8 to sca15 sub-cpu address high bits - symbol description comment xda0 to xda11 ram address bits, multiplexed for dram up to 16 mbytes dram only supported xras dram row address strobe xcas dram column address strobe xwr ram write enable xdd0 to xdd7 ram data bus symbol description comment syssync basic engine synchronization input generate interrupts on rising and/or falling edges comsync basic engine synchronization input generate interrupts on rising and/or falling edges comin receive data - comout transmit data - comclk serial data clock for synchronous mode - comack command acknowledge/transmit ?ow control must be high for synchronous mode to transmit next data byte symbol description comment 7 functional description the SAA7391 device consists of a number of main functional units; a cd engine interface, a multimedia block, a microcontroller interface, an error detection and correction block, a host interface and a memory manager. there are also several smaller blocks including a clock control block and a uart for communication with the cd engine. each block is independently controlled by a dedicated register set. these registers are memory mapped to the sub-cpu to allow for faster access. the external ram can also be accessed directly from the microcontroller to support scratchpad accesses and thus eliminate the need for further memory devices in the system. 7.1 memory ?eld description the cd input function of the SAA7391 buffer manager receives the main data stream in i 2 s-bus format from the cd-dsp, performs sync detection and partitions the data into blocks. it then writes the blocks to the buffer memory and onboard erco ram. any detected errors are then corrected and over written into the buffer memory. memory is segmented and addressable by segment pointers. the segment pointers consist of a block number, offset pointer and byte number within the block. the data within each segment is organised in the same manner (see table 10). the arrangement of data within each segment in memory differs from other philips devices, because of the different error correction processing possibilities within the SAA7391. addresses 0 to 2355 are written to memory by the drive processor when enabled.
1997 aug 01 16 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 10 the memory map of a block in the buffer ram for standard density mode (see table 11) table 11 description of table 10 address (offset) type of data 0 to 3 header ?eld 4 to 2339 block data ?eld 2340 to 2351 sync ?eld 2352 copy of stat0 2353 copy of stat1 2354 copy of stat2 2355 number of c2 ?ags in sector (compressed format) 2356 to 2451 96-byte de-interleaved r-w data ?eld 2452 to 2463 12-byte q-subcode ?eld 2464 to 2465 copy of stat4 ?eld; only valid if erco did run on this block 2466 to 2559 user work space data description header ?eld the 4-byte header data consists of a 3-byte block address of absolute time (minutes, seconds and frame, bytes 0 to 3). the fourth byte is for the mode of data: mode 0 = zero mode mode 1 = data storage with edc and ecc mode 2 = data storage block data ?eld in the cd-rom mode the block data consists of 2048 bytes of user data and 288 bytes of auxiliary data user data: mode 0= all 2048 bytes in user data are zero mode 1= all 2048 bytes are available to the user mode 2= all 2048 bytes are available to the user auxiliary data: mode 0= all 288 bytes in aux data are zero mode 1= the aux field is in accordance with the edc and ecc specification mode 2= all 288 bytes are available to the user sync ?eld the 12-byte sync ?eld is the next segment in memory. all bytes in the sync ?eld are ffh, except the ?rst and last bytes which are $00.
1997 aug 01 17 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.1.1 dvd-rom memory field information the buffer arrangement for dvd usage is basically the same (data followed by flags) but the size of the block data differs, and the erco flags are at a different offset, and as the erco is not in use, the flags relating to erco performance will not be valid. number of c2 ?ags in sector (compressed format) while storage of c2 ?ag positions is not possible as a consequence of the architecture of the SAA7391, a count of the number of ?ags seen per block is made in a single-byte counter. this counter packs the possibly 12-bit count into a single byte in the following way, at the expense of resolution in the count values for large counts. c2count_val = count (5 down to 0) [4 ^ count (7 down to 6)], the resolution of the count is therefore: c2count_val 0 to 63: counter resolution = 1 c2count_val 64 to 255: counter resolution = 4 c2count_val 256 to 1023: counter resolution = 16 c2count_val 1024 to 4095: counter resolution = 64 96-byte de-interleaved r-w data ?eld written to memory by the automatic q-channel copy process (copy2 channel). if the copy process is not enabled, these ?elds are not written (see section 7.3.5). these bytes may either be r-w de-interleaved or presented as raw q-w subcode bytes. if the copy2 interleaving mode is set to raw , interleaved copying is still required as the subcode temporary holding buffer has q bytes interspersed with the raw r-w. 12-byte q-subcode ?eld as above: these will not be separated out if the copy2 interleaving option is set to raw 2 copies of stat4 ?eld address 2465 and 2466 are copies of the stat4 register written by the erco when enabled. this allows the user to determine if the stat4 register has been written to by the erco. if seg2465 = seg2466 then stat4 de?nitely has not been written by the erco. if seg2465 1 seg2466 then stat4 probably has not been written by the erco. via direct access to buffer memory, the sub-cpu will be able to look at all of the blocks so far corrected, to check their status, in a background task. erco failures do not have to be dealt with immediately, as the status of every block loaded in to ram is stored with that block, and it is not overwritten until the ram block is ?lled with new data from cd input. the error corrector will be controlled additionally to permit the use of single pass p-q or only edc operation to allow for greater than n = 14 operation of the erco. the erco status will be copied into the ram along with the data. this is possible because the ram now has spare capacity to store the information, as part of the change from linear to segment/offset addressing. it is possible to program transfers into ram of more than one block without processor intervention. it is also possible to continually loop on the same buffer area of ram, by not altering the reload register values when the reload interrupt occurs. data description
1997 aug 01 18 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.2 cd input control registers the cd input process is intended to be as automated as possible. data is read in from the front end, descrambled if in cd-rom mode and then written to ram. the registers that control the address of where the data is written to are in the memory processor block. the input data is synchronized, decoded and written to the buffer ram. the input data format is software programmable. the synchronization is performed by using a sync detector and a sync interpolator. the sync detector can detect cd-rom syncs and syncs from the cflg pin, for use with red book, audio and for dvd. when no sync is found, it is optionally interpolated. after decoding, each full sector of data (2352 bytes) comprising sync, header and sub-header is written to the buffer ram. the r-w and q subcode is added by a software-initiated automatic block copy process. 7.2.1 r egisters associated with data in process table 12 ifconfig (write only; address ff10h) (see table 13) table 13 description of the ifconfig register bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ipcon?g ckdiv1 ckdiv0 subsel modulo 1 modulo 0 con?g swap con?g wclk bit name value meaning 7 ipcon?g 0 i 2 s-bus mode 1 eiaj serial interface mode 6 and 5 ckdiv1 and ckdiv0 00 oversample, bit clock division ratio = 2 01 oversample, bit clock division ratio = 4 10 oversample, bit clock division ratio = 8 11 bit clock division ratio = 1 (no division) 4 subsel 0 both copies of sub-header contribute to stat1/sh0err to sh3err 1 ?rst copy only of sub-header contributes to stat1/sh0err to sh3err 3 and 2 modulo 1 and modulo 0 00 modulo count 2352 01 10 modulo count 2064 11 modulo count 2064, but do not count bytes with ?ag = 1 1 con?g swap 0 the received data from the cd-dsp or drive fifo is not swapped 1 the received data from the cd-dsp or drive fifo is swapped 0 con?g wclk 0 the internal irclk is not inverted 1 the internal irclk is inverted
1997 aug 01 19 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 14 cd input control registers (see table 15) there are two sets of address registers, one giving the current (drivecurseg) number of the segment being filled and a segment/block counter. the other set contains the values (drivenextseg) to use on completion of the current group of blocks being filled or emptied (in cd-r). the driveprevseg register is loaded with the value of the drivecurseg register at the end of each cd-rom block. the reloading of the registers will trigger an interrupt, if enabled, of the sub-cpu, which will then have to reload the next registers. before the transfer requested in the current registers are exhausted. memory is split into segments, each segment is 2560 bytes. the drive data is written one block at a time at the segment number pointed to by the drivecurseg register. for the next block the drivecurseg is updated as follows. table 15 description of the incen and wren bits (see table 14) notes 1. if incen is logic 1, the drivecurseg pointer will increment every sector sync. the drivecurcount will decrement every sector sync independent of incen. if incen is logic 0 then the pointer will remain fixed pointing at the same segment of ram. if the reading of data from cd is enabled by the wrreq bit in the ctrl0 register, and the wren bit is logic 0 the segment will be repeatedly filled by the data coming in from the cd-rom. 2. if wren is logic 1 and incen is logic 1 then the drivecurseg register will increment with each sync time and the drivecurcount register will decrement but data will not be written to external ram. this allows the triggering of the reading of data or the writing of data some time in the future. table 16 control and status registers (see tables 17, 18 and 19) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff21h drivecurseg-l s7 s6 s5 s4 s3 s2 s1 s0 ff20h drivecurseg-h incen wren - s12 s11 s10 s9 s8 ff60h drivecurcount c7 c6 c5 c4 c3 c2 c1 c0 ff27h drivenextseg-l s7 s6 s5 s4 s3 s2 s1 s0 ff26h drivenextseg-h incen wren - s12 s11 s10 s9 s8 ff61h drivenextcount c7 c6 c5 c4 c3 c2 c1 c0 ff23h driveprevseg-l s7 s6 s5 s4 s3 s2 s1 s0 ff22h driveprevseg-h incen wren - s12 s11 s10 s9 s8 ff24h driveoffset-h s7 s6 s5 s4 s3 s2 s1 s0 ff25h driveoffset-l s7 s6 s5 s4 s3 s2 s1 s0 bit name value meaning 7 incen (1) 0 hold value of drivecurseg 1 increment drivecurseg at the end of each cd-rom block received 6 wren (2) 0 enable writes of data transferred 1 disable write of data transferred address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff0dh ctrl0 decen ahead e01rq autoform eramrq wrreq eccrq encode ff0eh ctrl1 syien syden asyn cowren onepass - - - ff0fh ctrl2 modrq formrq - automode mbckrq - dscren -
1997 aug 01 20 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 17 description of the ctrl0 register bits (resetting the chip sets all the bits in this register to 0) table 18 description of the ctrl1 register bits (the reset function clears all the ?ags in this register) bit name value description 7 decen 0 disable decoding, drive in full reset state, no monitor of i 2 s-bus line, no interrupts 1 enable decoding 6 ahead 0 obsolete 1 must be set to logic 1 5 e01rq 0 disable error correction of bytes for which an error has been detected, but not yet corrected 1 enable crc miscorrection correction of the c2 ?ag bytes 4 autoform 0 disable automatic form detection 1 enable automatic form detection 3 eramrq 0 disable erasure ?ag use 1 enable erasure ?ag use 2 wrreq 0 disable data writes to the buffer and pointer updates, only header and status information recovered 1 enables data writes to the buffer and pointer updates 1 eccrq 0 disable ecc correction only edc checking 1 enable ecc correction, erco active 0 encode 0 read operation 1 perform erasure correction on p and q check symbols, resulting in encoder operation bit name value description 7 syien 0 disable sync interpolation 1 enable sync interpolation 6 syden 0 disable sync detection 1 enable sync detection 5 asyn 0 cd-rom sync detection 1 audio sync detection 4 cowren 0 disable rewriting of corrected error bytes 1 enable rewriting of error bytes during error correction 3 onepass 0 normal error corrector operation 1 one pass only error correction
1997 aug 01 21 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 19 description of the ctrl2 register bits table 20 sub-cpu registers during read (see tables 21, 22, 23, 27 and 28) table 21 description of the stat0 register bits (resetting the chip clears all bits in this register) bit name value description 7 modrq 0 mode 1 request 1 mode 2 request 6 formrq 0 form 1 request 1 form 2 request 4 automode 0 disable automatic determination of mode bit 1 enable automatic determination of mode bit 3 mbckrq 0 disable mode check function 1 enable mode check function 1 dscren 0 disable descrambling function 1 enable descrambling function address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff00h head0 minutes ff01h head1 seconds ff02h head2 frames ff03h head3 mode ff04h subhead0 ?le number ff05h subhead1 channel number ff06h subhead2 submode ff07h subhead3 coding information ff08h stat0 - ilsync nosyn lblk - sblk erablk - ff09h stat1 minerr secerr blkerr moderr sh0err sh1err sh2err sh3err ff0ah stat2 rmod3 rmod2 rmod1 rmod0 mode form rform1 rform2 ff0bh stat3 valst - - - - - - - ff0ch stat4 crcok cblk uceblk - nocor mode form qok bit name value description 7 -- reserved - reserved 6 ilsync 0 - 1 sync pattern detected at word count 0 to 1174 5 nosyn 0 - 1 sync pattern inserted by sync interpolator not coincident with data sync 4 lblk 0 - 1 with syien at logic 0, no sync found; data block size has been extended 3 -- reserved - reserved
1997 aug 01 22 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 22 description of the stat1 register bits; address ff09h (see notes 1 and 2) notes 1. resetting the chip clears all bits in this register. 2. the bits in this register indicate the reliability of data in the head0 to head3 and subhead0 to subhead3 registers. 3. bits minerr, secerr, blkerr and moderr indicate errors in the minutes, seconds, frames and mode bytes in the header of the current block. 4. bits sh0err to sh3err indicate errors in the respective bytes in the subheader. table 23 description of the stat2 register bits; address ff0ah (see tables 24, 25 and 26) table 24 description of the mode and form bits table 25 description of the rform bits 2 sblk 0 - 1 short block indication 1 erablk 0 - 1 one or more bytes of the block are ?agged with c2 ?ags 0 -- reserved - reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 minerr (3) secerr (3) blkerr (3) moderr (3) sh0err (4) sh1err (4) sh2err (4) sh3err (4) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rmod3 rmod2 rmod1 rmod0 mode form rform1 rform2 mode form setting 0 0 mode 1 1 0 mode 2, form 1 x 1 mode 2, form 2 or ecc correction impossible rform1 rform2 meaning 0 0 form 1 0 1 form 2 1 x error in form byte bit name value description
1997 aug 01 23 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 26 description of the rmod bits note 1. rmod3 = bit 7 #, bit 6 #, bit 5 #, bit 4 #, bit 3 # of c2p0 (where # is logic or). this is non-zero for packet written cd-r. rmod2 = bi t 2 # cflg. rmod1 = bi t 1 # cflg. rmod0 = bi t 0 # cflg. table 27 description of the stat3 register bit table 28 description of the stat4 register bits (this register contains the interrupt status on reading) rmod3 to rmod30 (1) meaning 0000 mode 0 0001 mode 1 0010 mode 2 0011 mode 3 0100 mode 4 0101 mode 5 0110 mode 6 0111 mode 7 1xxx packet written cd-r, run in/run out, link, xxx is mode 1111 mode = 7 or error in mode byte bit name value description 7 valst 0 registers associated with decoder interrupt valid 1 registers invalid bit name value description 7 crcok 0 - 1 cyclic redundancy check ok 6 cblk 0 - 1 there has been an error in this block 5 uceblk 0 - 1 uncorrectable errors in block 4 - 0 reserved 1 reserved 3 nocor 0 - 1 erco was not started on this block 2 mode 0 mode 1 used in correcting this block 1 mode 2 used in correcting this block 1 form 0 form 1 used in correcting this block 1 form 2 used in correcting this block 0 qok 0 q channel crc no error 1 q channel crc error
1997 aug 01 24 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 29 auxiliary segment pointer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff29h auxsegment-l s7 s6 s5 s4 s3 s2 s1 s0 ff28h auxsegment-h - - - s12 s11 s10 s9 s8 the auxiliary segment pointer points at a group of segments which hold the data fifos used in the SAA7391. these are the large fifos rather than the small resynchronizing fifos inside the SAA7391. the subcode input/output and n = 1 i 2 s-bus interfaces use these fifos (in addition, the shadow debug registers can use some of this space). the fifos are arranged to optimally occupy a contiguous group of segments in the external ram. 7.3 multimedia output interface this block deals with subcode input and output in addition to an audio output which is independent of the i 2 s-bus input output path connected to the cd-r engine. q and r-w subcode features: supports semiautomatic de-interleaving/interleaving subcode sync is aligned with the start of the current block in ram supports subcode resynchronization when subcode sync is lost supports philips v4 and 3-wire formats (only one rck and one sfsy pin shared with subcode output) has selectable polarity on rck uses wsi1 pin as timing reference can insert p bit in 3-wire mode via sub-cpu accessible register bit supports regeneration of subcode from iec 958 output using ws2 as timing reference can accept subcode input while i 2 s-bus from cd-dsp is oversampled audio at n = 2 or n = 4 oversample subcode for cd-recordable applications is supported in philips v4 or 3-wire philips subcode recordable interface (sri). this sri mode is only compatible with cdr60. audio output (multimedia) features: has data output for simple audio or digital video for n = 1 or n = 2 rate regardless of input cd-dsp data rate 4096-byte fifo for audio samples, requires firmware polling for refills using the block copy engine permits cav and quasi-clv systems to maintain n = 1 audio output basic channel swap, mono-l or mono-r modes, includes muting and l + r summed mono iec 958 output with subcode q-w for use in cav and other modes where there is no n = 1 clock in the cd-dsp subsystem C iec 958 interface has fully programmable category code and copyright bits for flexibility C subcode on iec 958 is only available in cd-rom mode, because the subcode output fifo is shared. master and slave i 2 s-bus modes are available C iec 958 is only available when the i 2 s-bus is in the master mode. can be configured to provide a clock for an external cd-dsp function via the mck pin can operate in 64f s or 48f s i 2 s-bus modes iec 958 can operate at n = 2 although not permitted by standard. 7.3.1 s ubcode input block 7.3.1.1 q-w subcode handling the subcode data is initially converted from serial-to-parallel format and is then handled as q-w bytes. the de-interleaving is performed by a de-interleaving block copy mode in the memory processors block copy engine. subcode blocks will always be aligned with a block of cd-rom data, although the subcode minutes, seconds, frames (msf) absolute time may have an uncertainty of 5 frames in terms of the actual cd-rom block it is referring to. this offset is unknown but consistent in any given application. the block copy engine will be automatically triggered when the subcode synchronization is found. the error corrector will then compute the crc syndrome of the subcode and deposit it in the crc bytes. the sub-cpu will have to perform the actual correction if a non-zero syndrome appears. this syndrome, if calculated during encoding by the erco, can be used as the crc written to disc for the subcode.
1997 aug 01 25 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.3.1.2 description of subcode interface the subcode interface allows the reception and transmission of subcodes. the subcodes will be received/transmitted to two on-chip 512-byte fifos, one for transmit and one for receive. no interrupts are associated with these fifos as the block copy engine removes data or fills these as necessary. there is, however, an interrupt which is asserted when a sync is found in an unexpected location. 7.3.2 s ubcode mode transmit control register table 30 subcode mode transmit control register (submodetx; address ff13h); see table 31 table 31 description of the submodetx register bits note 1. philips v4 subcode transmit mode must be selected for correct insertion of subcode into the iec 958 data stream. for cd-recordable applications with cdr60 the philips sri subcode mode allows for correct subcode frame synchronization between the SAA7391 and the cdr60 device before recording commences. table 32 subcode mode receive control register (submoderx, address ff17h); see table 33 table 33 description of the submoderx register bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - pbit - txena - v4 bit name value description 4 pbit 0 p bit logic 1 in 3-wire mode (default) 1 p bit logic 0 in 3-wire mode 2 txena 0 subcode transmit interface is disabled 1 subcode transmit interface is enabled 0 v4 0 philips sri 3-wire subcode 1 philips v4 mode; note 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - wsdiv1 wsdiv0 rxena rckinvrx rxsubqw bit name value description 4 wsdiv1 00 no oversampling (normal cd-rom modes) 01 2 times oversampling 3 wsdiv0 10 4 times oversampling 11 8 times oversampling 2 rxena 0 subcode receive interface is disabled 1 subcode receive interface is enabled 1 rckinvrx 0 normal rck output 1 invert the rck output 0 rxsubqw 0 3-wire subcode 1 philips v4 mode (sub q-w)
1997 aug 01 26 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 34 subcode general (input/output pointers) 7.3.2.1 subcode buffering the subcode is buffered in the auxsegment register. two offset pointers, subpointr-l and subpointr-h, and subpointw-l and subpointw-h are associated with it. the r pointer is for the subcode output and the w pointer for the subcode input. pointers are also provided to point at the offset into the auxsegment register where the start of a subcode frame will be found, subbasepointr-l and subbasepointr-h and subbasepointw-l and subbasepointw-h. the block copy engine is expected to use these to automatically move the subcode into the segment pointed at by drivecurseg register. 7.3.3 g eneral description of the multimedia output interface table 35 multimedia output interface register bits notes 1. see table 36. 2. see table 39. 3. see table 38. 4. see table 41. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff2bh subpointr-l s7 s6 s5 s4 s3 s2 s1 s0 ff2ah subpointr-h - - - - - - - s8 ff2fh subpointw-l s7 s6 s5 s4 s3 s2 s1 s0 ff2eh subpointw-h - - - - - - - s8 ff2dh subbasepointr-l s7 s6 s5 s4 s3 s2 s1 s0 ff2ch subbasepointr-h - - - - - - - s8 ff31h subbasepointw-l s7 s6 s5 s4 s3 s2 s1 s0 ff30h subbasepointw-h - - - - - - - s8 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff32h cdda-h - - - - - - a9 a8 ff33h cdda-l a7 a6 a5 a4 a3 a2 a1 a0 ff34h daoffset-h - - - - a11 a10 a9 a8 ff35h daoffset-l a7 a6 a5 a4 a3 a2 a1 a0 ff16h mmctrl (1) mmdiv spdx2 wslen mcksel ff70h iecctrl (2) iecen data copyright preem vbit - accu ff71h ieccat cat7 cat6 cat5 cat4 cat3 cat2 cat1 cat0 ff14h mmaud (3) daen eiaj master - leftmode rightmode ff15h mck_con (4) - - - - mckxtal mckoe div
1997 aug 01 27 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.3.3.1 basic description of the multimedia output interface the multimedia data output may be used either with an internal clock or an externally provided clock. the clock used should be a correct multiple of 44100 hz in order for the block to correctly output iec 958. the multimedia interface data fifo is located in the block of segments associated with auxsegment master/slave mode operation (see fig.3). table 36 description of the mmctrl register bits bit name value description 7 mmdiv - see table 37 6 - 5 - 4 - 3 spdx2 0 i 2 s-bus output is single speed 1i 2 s-bus (and iec 958) output is double speed; video applications 2 wslen 0 i 2 s-bus bit clock is 64 times the sample rate 1i 2 s-bus bit clock is 48 times the sample rate 1 and 0 mcksel 00 multimedia internal clock is crin pin 01 multimedia internal clock is mck pin 10 multimedia internal clock is system clock fig.3 master/slave mode operation. handbook, full pagewidth mgk513 e.g. dac slave: master = 0 SAA7391 e.g. dac master: master = 1 SAA7391 sck ws sdo2 sck ws sdo2
1997 aug 01 28 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 37 mmdiv/mcksel relationship to clocks needed for i 2 s-bus and iec 958 notes 1. for these combinations the duty factor of the output sck2 clock is not necessarily 50%. these combinations are therefore not recommended. 2. this is illegal but possible. table 38 description of the mmaud register control bits note 1. if enabled, data is written to the cdda interface from a fifo located in the cdda register space. if either daen = 1 or iecen = 1 (ieccrtl), the interface will become active. divider code mmdiv mcksel i 2 s-bus output iec 958 i 2 s-bus, 48 bits per sample i 2 s-bus, 64 bits per sample multimedia clock oversample frequency (hz) n=1 n=2 n=1 n=2 n=1 (n=2) 0000 48f s 2116800 1 (1) - - - - - 0001 64f s 2822400 - - 1 (1) - - - 0010 96f s 4233600 2 1 (1) 1.5 (1) - - - 0011 128f s 5644800 - - 2 1 (1) 1 - 0100 192f s 8467200 4 2 3 1.5 (1) 1.5 - 0101 256f s 11289600 - - 4 2 2 (1) 0110 384f s 16934400 8 4 6 3 3 (1.5) (2) 0111 512f s 22579200 - - 8 4 4 (2) 1000 768f s 33868800 16 8 12 6 6 (3) 1001 1024f s 45158400 - - 16 8 8 (4) 1010 1536f s 67737600 32 16 24 12 12 (6) bit name value description 7 daen (1) 0 cd-da interface is off 1 cd-da interface is on 6 eiaj 0 i 2 s-bus serial mode 1 eiaj16 serial mode 5 master 0 i 2 s-bus is slave 1i 2 s-bus is master 3 leftmode 00 i 2 s-bus left channel output is left (default) 01 i 2 s-bus left channel output is right 210i 2 s-bus left channel output is muted 11 reserved 1 rightmode 00 i 2 s-bus right channel output is right (default). this is the opposite default to left channel. 01 i 2 s-bus right channel output is left 010i 2 s-bus right channel output is muted 11 reserved
1997 aug 01 29 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.3.4 iec 958/ebu output table 39 description of the iecctrl register control bits (notes 1 and 2) notes 1. in order for the iec interface to operate correctly, it will require a clock at 128f s to be present. 2. the vbit is copied into the v bit of the iec 958 frame. table 40 iec 958 system channel bit mapping (note 1) note 1. the c bit is updated on an iec frame-by-frame basis, the bit offset corresponds to the iec frame offset. they are repeated for both left and right channels. bit 0 is present in the c bit of the first sample pair of the iec superframe of 192 sample pairs. bit name value description 7 iecen 0 iec 958 interface is off 1 iec 958 interface is on 6 data 0 iec 958 contains audio information 1 iec 958 contains data 5 copyright 0 iec 958 c bit in system channel is logic 0 1 iec 958 c bit in system channel is logic 1 4 preem 0 audio pre-emphasis off/iec 958 contains data 1 audio pre-emphasis on (only appears in iec 958 c channel; de-emphasis bit is not implemented in the SAA7391) 3 vbit 0 audio samples suitable for conversion 1 mute audio, or signal is data and should not be digital-to-analog converted at any time 2 -- reserved - reserved 1 to 0 accu 00 level ii clock accuracy 01 level iii clock accuracy (depends on mck/system clock) 10 reserved 11 reserved bit number bit offset +0 +1 +2 +3 +4 +5 +6 +7 0 0 data copyright preem - 000 8 cat0 cat1 cat2 cat3 cat4 cat5 cat6 cat7 16 00000000 24 0000 accu0 accu1 0 0
1997 aug 01 30 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 41 description of the mck_con register bits (note 1) note 1. the bits in this register control the use of the mck pin as an output to clock a cd-dsp. the division ratios chosen are suitable for the saa7335 or cdr60 devices. if the mck pin is not being used then it should be pulled high for correct selection of the internal multimedia clocks. bit name value description 3 mckxtal 0 mck reference is system clock (default) 1 mck reference is the crin pin 2 mckoe 0 mck pin is 3-state, an input to the mm block (default) 1 mck pin is output 1 and 0 div 00 mck reference is divided by 2 (default) 01 mck reference is divided by 1.5 10 mck reference is divided by 1 11 mck reference is divided by 4 7.3.5 m emory - to - memory block copy function this function is provided for the user to move and copy blocks of ram. two pointer sets are provided. the second of these is for the semi-automatic subcode copying function of the subcode in the block. it is independent of the first copy register set, which is available for e.g. audio copying needed in the play audio function with the SAA7391, and for subcode copying when recording. when started, the copy process will copy the copycount register bytes from the from pointers to the to pointers. a copying process may be stopped during its operation by writing to the copyend bit. 7.3.5.1 automatic copying of received subcode-to-data block when enabled, the newly received subcode will be automatically transferred to the current host segment in ram. the only register that is user programmable in the subcode copying engine is the copyfrom2offset pointer. the copyfrom2offset pointer is set up by the sub-cpu to point into the subcode input fifo. it points at the first byte of subcode to be copied into the current host data block. once triggered, this copy is automatically set-up to correctly transfer the next block of subcode correctly without host intervention. copying of the subcode in the opposite direction is performed by the sub-cpu commanding an interleaved copy of data using the user block copy registers. this does not have to be as fast as the recorder function is only specified to n 3 8. hence it is not automated.
1997 aug 01 31 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 42 block copy registers note 1. see table 43. table 43 description of the copycontrol register bits address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff67h copycontrol (1) dfrom dto dfrom2 dto2 en1 en2 raw sub_deint_order ff3bh copyfromseg-l s7 s6 s5 s4 s3 s2 s1 s0 ff3ah copyfromseg-h - - - - s11 s10 s9 s8 ff37h copyfromoffset-l a7 a6 a5 a4 a3 a2 a1 a0 ff36h copyfromoffset-h - - - - a11 a10 a9 a8 ff3dh copytoseg-l s7 s6 s5 s4 s3 s2 s1 s0 ff3ch copytoseg-h - - - - s11 s10 s9 s8 ff39h copytooffset-l a7 a6 a5 a4 a3 a2 a1 a0 ff38h copytooffset-h - - - - a11 a10 a9 a8 ff63h copycount-l c7 c6 c5 c4 c3 c2 c1 c0 ff62h copycount-h - - - - c11 c10 c9 c8 ff3fh from2offset-l a7 a6 a5 a4 a3 a2 a1 a0 ff3eh from2offset-h - - - - a11 a10 a9 a8 ff41h to2offset-l a7 a6 a5 a4 a3 a2 a1 a0 ff40h to2offset-h - - - - a11 a10 a9 - bit name value description 7 dfrom 0 linear addressing with copyoffset 1 interleaved addressing with copyoffset 6 dto 0 linear addressing with copytooffset 1 interleaved addressing with copytooffset 5 dfrom2 0 linear addressing in copy from block, subcode copy engine 1 interleaved addressing in copy to block, subcode copy engine 4 dto2 0 linear addressing in copy to block, subcode copy engine 1 interleaved addressing in copy to block, user block copy engine 3 en1 0 user block copy disabled 1 user block copy enabled 2 en2 0 subcode block copy disabled 1 subcode block copy enabled 1 raw 0 enable complete subcode de-interleaving process 1 de-interleave r-w bytes, but skip q byte de-interleaving 0 sub_deint_order 0 de-interleave received subcode (cd-rom) 1 interleave transmitted subcode (cd-r)
1997 aug 01 32 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.4 interrupt registers the interrupt system in the SAA7391 is intended to make it possible to acknowledge interrupts both independently without interference or together. there are two interrupt pins to the sub-cpu from the SAA7391. the int pin is associated only with the host interface register ifstat (address ff92h). the int2 pin is associated with 6 interrupt registers which cover the SAA7391 drive block and uart. two status/reset registers and two interrupt enable register for the drive block and one status/reset register plus an interrupt enable register for the uart. table 44 ifstat interrupt register for the host interface; address ff92h (note 1) note 1. interrupt status bits are described in the host interface; see section 7.5.3.18. 7.4.1 i nterrupt 1 by writing a logic 1 to the int1reset register the bits will negate the int1status register bits. writing a logic 1 to an int1enable bit will enable the corresponding status bit. writing a logic 0 will disable the status to zero. table 45 int1status: drive interrupt register status; address ff7ah (see table 54) table 46 int1reset: drive interrupt register reset; address ff7ah (see table 54) 7.4.1.1 int1enable: drive interrupt register enable bits table 47 int1enable: drive interrupt register enable; address ff7bh (see table 54) access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r cmdi dtei drqi ultra_stop dtbsy srsti reset08 a0comp/ crc_error access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r dec nocor erablk cblk uceblk crc-ng q-ng int2 access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w dec nocor erablk cblk uceblk crc-ng q-ng - access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w dec nocor erablk cblk uceblk crc-ng q-ng int2
1997 aug 01 33 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.4.2 i nterrupt 2 by writing a logic 1 to int2reset register bits will negate the int2status bit. writing a logic 1 to an int2enable bit will enable the corresponding status bit. writing a logic 0 will disable the status to zero. table 48 int2status: drive interrupt register status; address ff7ch (see table 54) table 49 int2reset: drive interrupt register reset; address ff7ch (see table 54) table 50 int2enable: drive interrupt register enable; address ff7dh (see table 54) 7.4.3 uart interrupt by writing a logic 1 to the int2reset register bits will negate the int2status bit. writing a logic 1 to an int2enable bit will enable the corresponding status bit. writing a logic 0 will disable the status to zero. the int2 interrupt corresponds to not (int1 or int2 or uartint). table 51 uartintstatus: uart interrupt register status; address ff78h (see table 54) table 52 uartintreset: uart interrupt register reset; address ff78h (see table 54) table 53 uartintenable: uart interrupt register enable; address ff79h (see table 54) access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r hostbyte countzero drive reload hostrel countzero copyend subcode syncint dmatxint int1 uartint access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w hostbyte countzero drive reload hostrel countzero copyend subcode syncint dmatxini - - access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w hostbyte countzero drive reload hostrel countzero copyend subcode syncint dmatxini - - access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r comsync syssync notcomsync notsyssync nottxbfull rxbfull overrun rxparity access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w comsync syssync notcomsync notsyssync nottxbfull rxbfull overrun rxparity access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w comsync syssync notcomsync notsyssync nottxbfull rxbfull overrun rxparity
1997 aug 01 34 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 54 description of the interrupt register bits register interrupt description interrupt 1 dec block by block decoder interrupt nocor erco cannot be started on current block erablk one or more bytes coming from cd-dsp have been ?agged with error cblk corrected current block. uceblk one or more bytes remain in error crc-ng bad crc on current block q-ng bad q crc on current block int2 indicates that interrupt is caused by an enabled interrupt from int2 interrupt 2 hostbytecountzero the host counter decremented to zero and may have been reloaded; requires sub-cpu intervention when reload is disabled drivereload drive processing pointers have reloaded hostcursegcntzero the host reload count decremented to zero; no more host reloads are available copyend copy process has ?nished subcode syncint subcode receive block detection of early subcode 98 frame sync period dmatxint asserts when dmacount reaches zero with dmaon bit set int1 indicates that interrupt is caused by an enabled interrupt from int1 uartint indicates that the interrupt is from the uart interrupt register uart int comsync uart comsync pin rising edge interrupt syssync syssync pin rising edge interrupt notcomsync comsync falling edge interrupt notsyssync syssync pin falling edge interrupt nottxbfull transmit buffer has become empty rxbfull receive buffer has become full overrun receive buffer has overrun rxparity a character has been received with illegal parity 7.5 host interface 7.5.1 i ntroduction the SAA7391 host interface block is responsible for the transfer of data and control information between the memory processor, external host and microcontroller. the host interface operates in conjunction with the SAA7391 auxiliary block (aux block). the aux block contains several registers that automate the SAA7391 memory processor in its task of supplying the host interface with data from the buffer memory and receiving data from the host interface to be placed in the buffer memory. the host interface automates data transfer to and from the host, whereas the aux block automates data transfer, via the memory processor and buffer memory, depending on the cd format. the host interface features are as follows: supports ata packet interface (atapi revision 2.6) for cd-roms supports ata/atapi 16-bit pio data transfers for modes 0, 1, 2, 3 and 4 supports ata/atapi single/multi word dma transfers for modes 0, 1 and 2 supports ultra dma for mode 0 supports generic interface connection to external scsi controller device (ncr 53cf92) command and status registers of external generic interface controller are optionally mapped via the host interface pins of the SAA7391. the SAA7391 becomes the bus master. operates automatically with multi-block host data transfers
1997 aug 01 35 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 reduces microcontroller load in simple streaming transfers to or from host using a circular buffer recognizes ata srst, the atapi reset command (0x08) and the atapi packet command (0xa0) and handles these automatically in atapi mode handles unexpected ata commands during pio data transfers provides automatic drq for all pio data transfers provides automatic detection of atapi packet (a0) command and reception of the packet bytes provides automatic completion sequence for pio dma and ultra dma transfers supports shadowing of registers for single drive configurations with non-existent slave. 7.5.2 d escription of the host interface block the host interface block consists of three fifos which can be configured by the dtctr register to generate the required data path through the host interface block. the design supports atapi (revision 2.6) for cd-rom interfaces. the host interface has a shadow status register to permit proper ata operation. the pdiag and dasp signals are controlled by the register bits in the host interface block. the microcontroller has access to all registers in the host interface block. the microcontroller can control all operations required for data transfer to and from the host, but may configure the host interface sequencer to automate the following three operations: 1. automation of detection of the a0 packet command and reception of the 12-byte packet. 2. automation of the data transfer sequences for pio, dma and ultra dma modes of data transfer. 3. automation of completion sequences for pio, dma and ultra dma modes of data transfer. the host interface provides a generic interface mode for a glueless connection to an external scsi controller device. in this mode the microcontroller can configure the registers of the scsi controller device and initiate dma transfers. 7.5.2.1 the SAA7391 host interface atapi registers visible to the host table 55 host interface registers as seen from the host (note 1) note 1. the operation of these registers complies with the ata-3 specification (revision 6) and the atapi specification (revision 2.6). cs0 cs1 da2 da1 da0 host read ( dior) host write ( diow) 1 0 1 1 0 alt status: alternative status adctrl: atapi device control 1 0 1 1 1 adradr: atapi drive address not used 0 1 0 0 0 data: data register data: data register 0 1 0 0 1 aerr: atapi error register afeat: atapi features register 0 1 0 0 1 sherr: atapi error register (shadow) unused 0 1 0 1 0 aintr: atapi interrupt reason register unused 0 1 0 1 1 asamt: atapi sam tag register asamt: atapi sam tag register 0 1 1 0 0 dbcl: atapi byte count low dbcl: atapi byte count low 0 1 1 0 1 dbch: atapi byte count high dbch: atapi byte count high 0 1 1 1 0 adrsel: atapi drive select register adrsel: atapi drive select register 0 1 1 1 1 astat: atapi status register acmd: atapi command register 0 1 1 1 1 shstat: atapi status register (shadow) unused
1997 aug 01 36 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.2.2 the SAA7391 host interface registers visible by the microcontroller the registers listed in table 56 are used by the microcontroller to control the operation of the host interface block. the atapi command block registers (adata, astat, adradr, asamt, adrsel, aintr, aerr, acmd, adctr, afeat and apcmd) are dual port registers which can be accessed either by the microcontroller or the host pc depending the state of the bsy flag, bit 7 of the astat register. table 56 host registers as seen by the microcontroller addr access name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff80h w adata atapi data register ff81h rw ifctrl cmdien dteien drqien ultra_ stopien - srstien - - ff82h rw dbcl data byte count register (bits 7 to 0) ff83h rw dbch data byte count register (bits 15 to 8) ff84h w dtrg data transfer trigger register ff85h w dtack data transfer acknowledge register ff86h w reset reserved hsel ff87h rw astat atapi status register (see table 61) ff88h w itrg host interrupt trigger register ff89h w adradr atapi drive address register ff8ah rw asamt atapi sam tag register ff8bh rw dtctr reserved dmamode dma ultra_dma rdrv trant ff8ch rw adrsel atapi drive select register ff8dh rw aintr atapi interrupt reason register ff8eh rw aerr atapi error register ff8fh r acmd atapi command register ff90h r adctr atapi device control register ff91h r afeat atapi features register ff92h rw ifstat cmdi dtei drqi ultra_stop dtbsy srsti reset08 a0comp/ crc_error ff93h r apcmd atapi packet command register ff94h rw hiconf0 ultractrl2 to ultractrl0 dynhosthiprior hrequest shadow ff95h rw hiconf1 dmaen shhpbit udmaoff ?ush?fo - unmaskdtie clear_reg ultractrl3 ff96h rw hiseq autoa0 autodrq comp error sus_seq repeat autoa0 - - ff97h rw shstat 0 0 0 0 0 0 0 shcheck
1997 aug 01 37 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 ff98h rw sherr 0 0 0 0 0 shabrt 0 0 ff99h rw hidev pdiag out pdiag pad enable dasp out dasp pad enable pdiag in dasp in - hosthipi ff9ah r histat not used ffa0h rw transfer counter byte count (bits 7 to 0) ffa1h rw transfer counter byte count (bits 15 to 8) ffa2h rw transfer counter byte count (bits 23 to 16) ffa3h rw transfer counter byte count (bits 31 to 24) ffa4h rw packetsize store byte count (bits 7 to 0) ffa5h rw packetsize store byte count (bits 15 to 8) ffa6h r sequencer _status - - sequence state (bits 5 to 0) addr access name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1997 aug 01 38 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.3 d escription of the host interface registers this section describes the operation of the register bits in the SAA7391 host interface block. 7.5.3.1 adata this is a 12-byte fifo used to transfer data from the microcontroller to the host. to transfer data the trant bits (0 to 2) of the dtctr register must be set to 101. 7.5.3.2 ifctrl table 57 ifctrl: address ff81h (note 1) note 1. bits cmdien, dteien, drqien and ultra_stopien, are the enable bits for interrupt bits cmdi, dtei, drqi and ultra_stop in the ifstat register. these are interrupt masks, enabling/disabling the microcontroller interrupt pin. they do not affect the bits in the ifstat register. if set to logic 1, the corresponding interrupt is enabled. it should be noted that these masks do not clear the interrupts. bit 2 ( srstien) is asserted at power-on reset, enabling the srsti interrupt. if set to logic 1 the srsti interrupt is disabled. 7.5.3.3 dbcl and dbch these are the atapi byte count registers. dbcl is the lower byte (bits 7 to 0) register and dbch is the higher byte (bits 15 to 8) register. these registers are read/writable for both the pc host and microcontroller. table 58 atapi byte count registers; addresses ff82h (dbcl) and ff83h dbch) the data byte counter is used by the microcontroller to control the number of bytes that are transferred during a data transfer. during memory-to-host data transfers the data byte counter is decremented after every host read. during host-to-memory data transfers the data byte counter is decremented as data is written into the external buffer memory. the host may write to dbcl/dbch to indicate to the microcontroller the maximum transfer/reception length, which may be updated by the auto sequencer packetsize store registers or from the transfer counter (for the remainder packet size) or directly by the microcontroller. the host can then read back the updated byte count to be transferred. 7.5.3.4 dtrg writing to this register starts a data transfer. the data written is discarded. 7.5.3.5 dtack writing to this register clears the dtei interrupt and the a0comp/crc_error flag. the data written is discarded. access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw cmdien dteien drqien ultra_stopien - srstien - - access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw data byte count register bits (bits 7 to 0) rw data byte count register bits (bits 15 to 8)
1997 aug 01 39 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.3.6 reset writing to this register resets the SAA7391 and initializes all the registers on the device. table 59 reset; address ff86h (note 1) note 1. the hsel bits (see table 60) control the mode of operation of the host interface block. after a power-on reset the hsel bits default to 000, i.e. the host 3-state pins are 3-stated. the firmware must configure the hsel bits for the desired mode of operation after every hardware reset. it should be noted that any write operation by the microcontroller to this register will result in the resetting of all other SAA7391 registers to their default condition. table 60 description of the hsel bits 7.5.3.7 astat this is the atapi status register. table 61 astat: address ff87h (notes 1 and 2) notes 1. the bsy flag bit 7 will be set to logic 1 when: a) the host writes to the acmd register and the SAA7391 is the selected drive. b) the host writes the execute drive diagnostic command (90h) to the acmd register. c) the host writes to the adctr register and sets the srst bit. d) there is a hardware reset. 2. if a host interrupt is asserted then it will be cleared by writing to this register. 7.5.3.8 itrg in the atapi mode writing to this register generates a pc host interrupt on the int pin. this interrupt is cleared when the pc host reads the atapi status register (astat) or writes to the atapi command register. 7.5.3.9 adradr this is the atapi drive address register for the SAA7391. this uses an obsolete register address ( cs1 ? da0 = 10111) from the atapi register map in the atapi specification. bit 7 of this register is high-impedance when read by the host. after a reset the atapi registers are all cleared except for the astat register which has its bsy bit set. access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w reserved hsel hsel2 to hsel0 host interface mode description 000 unknown host all host pins 3-state, default after hardware reset 001 atapi atapi interface mode 011 generic 8-bit generic interface mode, with 8-bit transfers 100 generic 16-bit generic interface mode, with 16-bit transfers others reserved for future enhancements access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw bsy drdy dmar dsc drq corr reset check
1997 aug 01 40 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.3.10 asamt this is the atapi sam tag byte register. 7.5.3.11 dtctr the dtctr register controls data transfer flows in the host interface block. when reset this register is cleared to all zeros except for the rdrv bit which is set to logic 1. this means the SAA7391 will be then set to device 1 (slave) after a reset. there are several possible data transfers through the SAA7391 host interface block and these are selected using the trant bits. the transfers are described in table 64. table 62 dtctr: address ff8bh (see tables 63 and 64) table 63 description of the dtctr register bits access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw reserved dmamode dma ultra_dma rdrv trant bit name description 6 dmamode dma mode select; controls whether the dma transfer is single word or multi-word dmamode = 1; host interface dma data transfers are multi-word dmamode = 0; host interface dma data transfers single word 5 dma this bit is used to configure the SAA7391 hardware for either a dma type transfer or a pio type transfer dma = 1; configures the SAA7391 for a dma transfer dma = 0; configures the SAA7391 for a pio type transfer 4 ultra_dma this bit configures the SAA7391 for ultra dma transfers; the SAA7391 must also be configured for multi-word dma transfers for correct operation of ultra dma i.e. bits 5 and 6 of the dtctr register must also be set to logic 1 to select ultra dma ultra_dma = 1; configure the SAA7391 for ultra dma (must be select dma = 1 and dmamode = 1) ultra_dma = 0; default for non-ultra dma transfers 3 rdrv this bit selects the device number: the polarity of this bit must be the same as the drv bit in the atapi drive select register (adrsel) in order for the SAA7391 to communicate with the pc host interface; after reset the microcontroller should configure the rdrv bit as no default may be assumed. rdrv = 1; the SAA7391 is device 1 i.e slave rdrv = 0; the SAA7391 is device 0 i.e master
1997 aug 01 41 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 64 description of the trant bits 7.5.3.12 adrsel this is the atapi drive select register. table 65 adrsel: address ff8ch note 1. bit 4 of this register is the drv bit. when this bit is the same as the rdrv bit in the dtctr register then the SAA7391 will be the selected atapi drive and will respond to commands and produce interrupts. the host interrupt pin will also be enabled when the SAA7391 is the selected drive. 7.5.3.13 aintr this is the atapi interrupt reason register. see the atapi specification for a detailed description of these register bits. table 66 aintr: address ff8dh 7.5.3.14 aerr this is the atapi error register. see the atapi specification for a detailed description of these register bits. table 67 aerr: address ff8eh trant (bits 2 to 0) from to maximum bytes notes 000 - host 65535 (atapi, pio) maximum bytes for auto sequence dma is 4.3 gbytes 001 host memory 65535 (atapi, pio) maximum bytes for auto sequence dma is 4.3 gbytes 010 microcontroller memory - redundant 011 memory microcontroller - redundant 100 host microcontroller 12 pio; dbc not used, always 12 bytes 101 microcontroller host 12 dma and pio 11x reserved reserved reserved - access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw 1 1 1 drv (1) ---- access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw ----- release io cod access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw sense key mcr abrt eom -
1997 aug 01 42 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.3.15 acmd this is the atapi command register. this register is read-only to the microcontroller and write-only to the host. the host should only write to this register when the bsy and drq flags are both zero (see astat register; section 7.5.3.7). a cmdi interrupt is generated when: the host writes to this register while the SAA7391 is the selected drive (the drv bit in register adrsel is equal to the rdrv bit in register dtctr) the host writes the execute drive diagnostic command (90h) to this register. the microcontroller interrupt (cmdi) is cleared by the SAA7391 when the acmd register is read by the microcontroller. 7.5.3.16 adctr this is the atapi device control register. table 68 adctr: address ff90h notes 1. setting the srst bit causes a srsti interrupt and the bsy bit to be set. 2. bit nien is used to enable or disable the host interrupt. when nien is logic 0 and the drive is selected then the host interrupt pin will be enabled. if nien is logic 1 or the drive is not selected then the host interrupt pin will be in a high-impedance state. 7.5.3.17 afeat this is the atapi features register. see the atapi specification for a detailed description of these register bits. table 69 afeat: address ff91h 7.5.3.18 ifstat table 70 ifstat: address ff92h (note 1); see table 71 notes 1. all interrupts may be negated by writing a logic 1 to their associated ifstat locations. 2. these bits are flags which do not generate interrupts. access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r reserved 1 srst (1) nien (2) 0 access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r - - - - - - overlap dma access bit 7 bit 6 bit 5 bit 4 bit 3 (2) bit 2 bit 1 (2) bit 0 (2) rw cmdi dtei drqi ultra_stop dtbsy srsti reset08 a0comp/ crc_error
1997 aug 01 43 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 71 description of the ifstat register bits 7.5.3.19 apcmd during the atapi mode this register is used to read the packet command sent by the host. the packet command can only be received if the appropriate mode has been selected (see dtctr register; table 62) and a data transfer has been started (see dtrg register; see table 56). bit name description 7 cmdi command interrupt: in the atapi mode this bit is asserted when the pc host has written to the atapi command register (see acmd register; section 7.5.3.15) and the drive is selected. it is also asserted when the host writes the execute drive diagnostic command (90h) to the atapi command register, regardless of whether the drive is selected. it is negated when the microcontroller reads the acmd register or writes logic 1 to cmdi. 6 dtei data transfer end interrupt: this bit is asserted at the end of data transfer. it is negated when the microcontroller writes to the dtack register or writes logic 1 to dtei. if the atapi mode is selected this bit is also asserted when a packet command has been received and after a microcontroller memory transfer. the interrupt generated by this bit can be masked by the auto sequencer. 5 drqi auto sequencer data request interrupt: if enabled by drqien (ifctrl; see table 57), this bit is asserted after every load of the packet size store into dbch/dbcl during an autodrq dma sequence. drqi is cleared along with its associated interrupt by the microcontroller writing logic 1 to drqi. 4 ultra_stop ultra ata stop before end of transfer interrupt: if enabled by ultra_stopien (ifctrl; see table 57), this bit is asserted if the host stops an ultra ata data transfer before the transfer counter has reached zero, when autodrq is selected, or before the dbch/dbcl task file registers reach zero when autodrq is not selected. ultra_stop is cleared along with its associated interrupt by the microcontroller writing logic 1 to ultra_stop (ifstat; see table 70). 3 dtbsy data transfer busy: this bit indicates if a data transfer is taking place. it is asserted by writing to the dtrg register and is negated at the end of the transfer. 2 srsti interrupt/status transfer busy: in atapi mode this bit is asserted when the host writes to the atapi device control register and sets the srsti bit. it is negated when the microcontroller reads the adctr register or by writing a logic 1 to the srst (adctr; see table 68). it should be noted that if this bit is asserted in the atapi mode then the microcontroller interrupt will also be asserted. the srsti interrupt cannot be disabled. 1 reset08 the reset command 08 has been received: this bit indicates that the last command received was the 08 reset command. reading the command register acmd will negate this bit and its associated interrupt. 0 a0comp/ crc_error the a0 command auto sequence is completed or ultra ata crc error flag: this bit indicates that a0 command auto sequence is completed i.e. the correct a0 command has been read and the host interface has been configured to receive the 12 byte packet. this bit does generate an interrupt but should be used in conjunction with the dtei interrupt. a microcontroller write to dtack will negate the a0comp bit. after an ultra dma data transfer (read from the SAA7391 or write to the SAA7391) this bit may be used in conjunction with the dtei interrupt to indicate data integrity. if the crc_error bit = 0 then the last data transfer was corrupt. again writing to dtack will negate this bit.
1997 aug 01 44 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.3.20 hiconf0 this is the host interface con?guration register 0 table 72 hiconf0: address ff94h table 73 description of the hiconf0 register bits 7.5.3.21 hiconf1 this is the host interface con?guration register 1. table 74 hiconf1: address ff95h (see table 75) access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw ultractrl2 to ultractrl0 dynhosthiprior hrequest shadow bit name description 7 to 5 ultractrl2 to ultractrl0 ultra control bits (3 to 1), see section 7.5.3.22 4 dynhosthiprior dynhosthiprior (1) 0 = n = dynamic host high priority asserted when fifo is 1 3 full 1 = n = dynamic host high priority asserted when fifo is 1 2 full 3 dynhosthiprior dynhosthiprior (0) 0 = (default) dynamic host high priority off 1 = dynamic host high priority on when fifo bytes, n, off when > n 2 and 1 hrequest hrequest = 00; (default) assert host request when fifo 2 3 full hrequest = 01; assert host request when fifo 1 2 full hrequest = 10; assert host request when fifo 1 3 full hrequest = 11; assert host request when fifo (full - 2 bytes) 0 shadow shadow enable: this bit controls whether shadowing of single drive configurations is enabled shadow = 1; enables shadowing for single drive configurations when the SAA7391 is master and slave is non existent shadow = 0; disables shadowing access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw dmaen shhpbit udmaoff ?ush?fo - unmaskdtei clear_reg ultractrl3
1997 aug 01 45 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 75 description of the hiconf1 register bits bit name description 7 dmaen dma suspend: this bit controls whether dma transfers in generic mode are suspended dmaen = 1; host interface dma data transfers in generic can be temporarily interrupted dmaen = 0; host interface dma data transfers in generic mode cannot be suspended 6 shhpbit this bit allows statistical host high priority to be turned off shhpbit = 0; (default) statistical host high priority turned on shhpbit = 1; statistical host high priority turned off 5 udmaoff this bit allows udma to be turned off at the end of a transfer udmaoff = 0; (default) switch off the ultra_ata bit in the dtctr register udmaoff = 1; do nothing 4 flush?fo flush 12-byte command fifo: writing a logic 1 to this bit will flush clear the command fifo pointer to zero. clearing the pointer is required if a spurious command is received while the fifo is being loaded and is also used to ensure a 12-byte command read by the auto sequencer. flush?fo = 1; writing a logic 1 clears the fifo pointer to zero flush?fo = 0; do nothing 2 unmaskdtei unmask data transfer end interrupt during autodrq sequence: this bit will disable the auto sequencer masking of the dtei interrupts during the autodrq sequence. the dtei, bit 6 of the ifstat register is not effected by unmaskdtei. if unmaskdtei is asserted the sequencer on detecting the next dtei interrupt, will set the bsy flag, negate the drq flag and suspend operation. the microcontroller may then reconfigure the host interface before negating unmaskdtei bit. when unmaskdtei is negated the sequencer will negate the dtei interrupt and operate as normal. unmaskdtei = 1; disable autodrq sequencer masking of dtei interrupts and suspend the sequence operation on next dtei interrupt unmaskdtei = 0; no effect, or restart autodrq sequencer operation 1 clear_reg clear auto sequencer transfer counter and packet size store to zero: this bit will clear the transfer counter and packet size store to zero if a logic 1 is written to it. after the write operation the registers operate as normal and the clear_reg bit will have no effect unless written to again. clear_reg = 1; clears to zero transfer counter and packet size store clear_reg = 0; no effect 0 ultractrl3 ultra control bit 3; see section 7.5.3.22
1997 aug 01 46 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.3.22 description of the ultra control bits the ultractrl register bits can be used to add system clock cycles to various timing limits used in the host interface ultra dma transfer engine. this enables the SAA7391 to meet ultra dma mode 0 timings when the SAA7391 system clock is higher than 33.8688 mhz. when the SAA7391 system clock is 33.8688 mhz, maximum data transfer rates in ultra dma mode 0 are achieved by setting ultractrl to (0001). for information on meeting mode 0 timings for system clocks other than 33.8688 mhz, please consult the user manual or product support. 7.5.3.23 hiseq table 76 hiseq: host interface sequencer register; address ff96h (see table 77) table 77 description of the hiseq register bits access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw autoa0 autodrq comp error sus_seq repeat autoa0 - - bit name description 7 autoa0 automatic a0 packet transfer enable: this bit enables the sequencer to automatically handle transfer of a0 packet bytes autoa0 = 1; enables automatic transfer of a0 packet bytes autoa0 = 0; disables automatic transfer of a0 packet bytes 6 autodrq enables the auto data request sequence: this bit enables automatic handling of data requests in pio and dma mode transfers autodrq = 1; auto sequencer is enabled to perform auto data requests autodrq = 0; auto sequencer is not enabled to perform auto data request 5 comp completion sequence for autodrq: this bit indicates that the auto completion sequence should be performed after the last data transfer. this bit is only valid when the auto sequencer is enabled. comp = 1; enable the auto sequencer to automate the completion sequence comp = 0; disable the auto completion sequence 4 error completion sequence with error status: this bit is copied to the check bit of the astat register just before an auto completion sequence is performed error = 1; completion sequence with error status in check bit of astat error = 0; completion without error status 3 sus_seq suspend auto sequence: this bit suspends the auto sequencer for debug. if the suspend state is a write to register state then the write operation will only take place when after the sus_seq bit is negated. sus_seq = 1; suspend sequencer in present state sus_seq = 0; normal sequence operation 2 repeat autoa0 repeat the a0 packet reception auto sequence after an autodrq or auto completion sequence. this bit, if set before an autodrq or auto completion sequence, will be copied to autoa0 bit when the sequencer is reset at the end of an autodrq or auto completion sequence. this bit is negated at the end of the autoa0 sequence. its effect is to repeat the autoa0 sequence one more time only. it should be noted that this bit is only available on rodap and not the m1 data base. repeat autoa0 = 1; repeat autoa0 sequencer after autodrq or auto completion repeat autoa0 = 0; no effect
1997 aug 01 47 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.3.24 shstat table 78 shstat: shadow status register; address ff97h note 1. shadow check bit: shcheck is the atapi check bit in the slave shadow status register for the non-existent drive. a) 1 = indicates an error has occurred. b) 0 = indicates no error has occurred. 7.5.3.25 sherr table 79 sherr: shadow error register; address ff98h note 1. shadow abort bit: shabrt is the atapi abrt bit in the slave shadow error register for the non-existent drive. this bit will be read by the host in shadow mode only. a) 1 = indicates requested command has been aborted. b) 0 = indicates requested command successful. 7.5.3.26 hidev table 80 hidev: host interface device register; address ff99h (see table 81) access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0 0 0 0 0 0 0 shcheck (1) access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w 0 0 0 0 0 shabrt (1) 0 0 access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw pdiag out pdiag enable dasp out dasp enable pdiag in dasp in - hosthipi
1997 aug 01 48 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 81 description of the hidev register bits bit name description 7 pdiag out this bit is the passed diagnostics signal output from the SAA7391 pdiag out = 1; writing logic 1 to this bit drives the pdiag pin high if the pad enable (pdiag enable bit 6) is set to logic 1. it is recommended that this bit is written low and that the enable bit is driven to emulate an open-collector output. pdiag out = 0; writing logic 0 to this bit sets the pdiag pin low if the pad enable (pdiag enable bit 6) is set to logic 1 6 pdiag pad enable this bit default is an input to the SAA7391 pdiag pad enable = 1; writing logic 1 to this bit enables the pdiag driver output of the SAA7391 pdiag pad enable = 0; default on power-up allowing external control of the pdiag in bit 3 5 dasp out this bit is the device active slave present signal output. this pin is open-collector with an external pull-up resistor. the dasp bit must be set to logic 1 in order to determine if any other device is driving this signal. dasp out = 1; writing logic 1 to this bit drives dasp high if the pad enable (dasp enable bit 4) is set to logic 1. it is recommended that this bit is written low and that the enable bit is driven to emulate an open-collector output. dasp out = 0; writing logic 0 to this bit sets the dasp pin low if the pad enable (dasp enable bit 4) is set to logic 1 4 dasp pad enable this bit default is an input to the SAA7391 dasp pad enable = 1; writing logic 1 to this bit enables the dasp driver output of the SAA7391 dasp pad enable = 0; default on power-up allowing external control of the dasp in bit 2 3 pdiag in this bit is the passed diagnostics signal input to the SAA7391, only valid if pdiag enable bit 6 is set to logic 0 (default = 0) 2 dasp in this bit is the device active slave present signal input to the SAA7391, only valid if dasp enable bit 4 is set to logic 0 (default = 0) 0 hosthipi this bit allows the host interface to increase its priority rating when requesting a data transfer between itself and the SAA7391 memory processor. with host high priority set the host data transfer requests are given the second highest priority, the highest given to the microcontroller. hosthipi = 1; writing logic 1 increase host interface priority above all other data transfer requests, bar the microcontroller. hosthipi = 0; writing logic 0 to this bit (default setting) gives low priority to the host interface data transfer request.
1997 aug 01 49 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.4 t ransfer counter the transfer counter register defines the total transfer length to be transferred to or from the host. this register is loaded by the microcontroller and decrements synchronously with the dbch/dbcl registers. the remainder packet size can be loaded from the transfer counter into dbch or dbcl when the transfer counter value becomes less than the packet size store. table 82 transfer counter register 7.5.5 p acket size store the packet size store will be loaded from the dbch or dbcl registers when the host writes to acmd, provided the drive is selected. it may also be updated by the microcontroller. the dbch/dbcl registers will be auto loaded from the packet size store on condition that the transfer counter contains an equal or greater value than that held in the packet size store. table 83 packet size store 7.5.6 s equencer status 7.5.6.1 sequencer status for debugging the auto sequencer a sequencer status register has been provided (address ff6ah). a suspend sequence bit has been provided (hiseq bit 4; see table 76), which if asserted (logic 1) will suspend the auto sequencer operation at its present state. the suspended state may then be read from the sequencer state register. if the sequencer state is a write to a host interface registers state, then the sequencer will perform the write operation after the suspend sequencer bit is negated by the microcontroller. table 84 sequencer status: address ffa6h (note 1) note 1. for an explanation of the sequence state number see the user guide. the user guide is available from product support. address access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ffa0h rw byte count (bits 7 to 0) ffa1h rw byte count (bits 15 to 8) ffa2h rw byte count (bits 23 to 16) ffa3h rw byte count (bits 31 to 24) address access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ffa4h rw byte count (bits 7 to 0) ffa5h rw byte count (bits 15 to 8) access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r - - sequencer state (bits 5 to 0)
1997 aug 01 50 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.6.2 auxiliary block memory processor registers the registers given in table 85 are located in the aux block of the and control the SAA7391 memory processor buffer management. transfer to/from the host is possible as soon as the hostbytecount is non-zero, and the hostcursegcnt is non-zero. the chan0 and chan1 bits control the sequencing of sub-block transfers. they indicate the number of offset/length pairs to use for each block being transferred. normally only channels 0 and 1 are needed for mode 2 host transfers. channels 2 and 3 are available for special read-cd command options. an interrupt is associated with hostbytecount becoming zero. this is an indication to the microcontroller to reload the hostcurseg and hostbytecount registers for the next transfer. the hostcurseg, hostbyteoffset and hostbytecount registers indicate the address of the next byte to be transferred to or from the host, in order that the status of the interface may be read. the operation of the hostbytecount and hostbyteoffset registers is given in table 85. table 85 host interface dma pointers addr access name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff45h rw hostcurseg-l s7 s6 s5 s4 s3 s2 s1 s0 ff44h rw hostcurseg-h chan1 chan0 - s12 s11 s10 s9 s8 ff66h rw hostcursegcnt b7 b6 b5 b4 b3 b2 b1 b0 ff59h rw hostsubblkoffset0-l a7 a6 a5 a4 a3 a2 a1 a0 ff58h rw hostsubblkoffset0-h autoform form - - a11 a10 a9 a8 ff5dh rw hostsubblkoffset1-l a7 a6 a5 a4 a3 a2 a1 a0 ff5ch rw hostsubblkoffset1-h autoform form - - a11 a10 a9 a8 ff51h rw hostsubblkoffset2-l a7 a6 a5 a4 a3 a2 a1 a0 ff50h rw hostsubblkoffset2-h autoform form - - a11 a10 a9 a8 ff55h rw hostnextseg-l a7 a6 a5 a4 a3 a2 a1 a0 ff54h rw hostnextseg-h autoform form - a12 a11 a10 a9 a8 ff5bh rw hostsubblkcount0-l c7 c6 c5 c4 c3 c2 c1 c0 ff5ah rw hostsubblkcount0-h - - - - c11 c10 c9 c8 ff5fh rw hostsubblkcount1-l c7 c6 c5 c4 c3 c2 c1 c0 ff5eh rw hostsubblkcount1-h - - - - c11 c10 c9 c8 ff53h rw hostsubblkcount2-l c7 c6 c5 c4 c3 c2 c1 c0 ff52h rw hostsubblkcount2-h - - - - c11 c10 c9 c8 ff57h rw hostnextsegcount c7 c6 c5 c4 c3 c2 c1 c0 ff56h rw hostreloadflags rel1 rel2 -- c11 c10 c9 c8 ff43h rw hostbyteoffset-l a7 a6 a5 a4 a3 a2 a1 a0 ff42h rw hostbyteoffset-h autoform form -- a11 a10 a9 a8 ff65h rw hostbytecount-l c7 c6 c5 c4 c3 c2 c1 c0 ff64h rw hostbytecount-h - - - - c11 c10 c9 c8 ff69h rw hostrelseg-l s7 s6 s5 s4 s3 s2 s1 s0 ff68h rw hostrelseg-h chan1 chan0 - s12 s11 s10 s9 s8 ff6bh rw aux_form_scan c7 c6 c5 c4 c3 c2 c1 c0
1997 aug 01 51 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 86 decoding chan bits 7.5.7 h ost interface dma special bits table 87 decoding bits 7 and 6 of hostsubblkoffsetx-h (note 1) note 1. the last form bit is the lsb of the byte that is situated at offset 12 in the current segment pointed at by hostcurseg. this is the stored form byte in the header. value description 00 use extent 0 01 use extent 0 to 1 10 use extent 0 to 2 11 use extent 0 to 3 (see also section 7.5.8) bit name value description 7 autoform 0 unconditional transfer 1 only transfer if previous form bit matches bit 6 6 form 0 match last form bit = 0, perform this transfer if success else reload host registers 1 match last form bit = 1, perform this transfer if success else reload host registers 7.5.8 a utomatic block pointer reload programming if either bit 6 or bit 7 are set in the hostreloadflags register, then when the hostreloadcount register becomes zero, the value of hostcursegcnt will be copied from hostnextsegcount and hostrelsegment will be copied from hostnextseg. this causes the host transfer process to continue looping over the same region of memory in emulation of the chaucer and sequioia devices. at the same time one of the bits hostreloadflags (bits 7 and 6) is reset on reload of the registers. the other bit retains its value. therefore: single auto-reload is allowed: hostreloadflags (bits 7 and 6) = 1 0 no auto-reload: hostreloadflags (bits 7 and 6) = 0 0; pointer can be used as sub-block extent 3 multiple auto-reload: hostreloadflags (bits 7 and 6) = 0 1. 7.5.9 dma transfer programming of the host interface the host interface is optimized for the normal read commands, handling all data transfers or contiguous data plus header requests automatically, with auto form detection in mode 2. if discontinuous data which requires more than 3 sub-block extents e.g. for read-cd is required then it is necessary to program the hostcurseg, hostbytecount and hostbyteoffset for each discontinuous part of each block that is to be transferred. writing the value 1 into the hostblock will cause the transfer to take place.
1997 aug 01 52 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.10 g eneric interface operation implementation of the generic interface with the ncr 53cf92 in a multiplexed bus configuration is shown in fig.4. the host interface, after power-up, needs to be configured for the scsi controller by writing the value 3 to the reset register (address ff86h) for an 8-bit data transfer configuration and the value 4 for a 16-bit data transfer configuration. the ncr 53cf92 device is configured by tying its mode pin to ground. in this mode the ncr 53cf92 device expects from the microcontroller a multiplexed address/data bus. multiplexed address/data bus is the only mode supported by the SAA7391. the active low chip select (cs) signal from the SAA7391 is generated by the host interface. there are 32 specific scsi addresses in the SAA7391 memory map, between location ffc0h and ffdfh. the cs pin will be active low for addresses in this range. the standard register set on the ncr 53cf92 contains 16 registers which are accessed when the cs is true. the specific register being accessed is determined by the states of the rd and wr signals together with the address pins a3 to a0. fig.4 generic interface connection to ncr 53cf92 in multiplexed mode. handbook, full pagewidth mgk508 ncr 53cf92 dreq dack dbwr db7 to db0 a0 a1 a2/dbrd a3/ale cs rd wr mode SAA7391 dmack/dmarq dmarq/dmack dd0 to dd7 microcontroller da1/dbwr da2/dbrd cs0/scsics 8051 8-bit address/data bus 8-bit dma bus
1997 aug 01 53 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.5.11 dma transfers in generic mode the host interface in generic mode will support two types of dma transfer to the ncr device, namely: normal dma mode burst dma mode. both of these modes are 8 bit dma transfers. during data transfers the microcontroller can suspend the dma transfer (via hiconf1 register dmaen bit 7) under the following conditions: an interrupt received an abort received a register read required. 7.5.12 n ormal dma mode in this mode the host interface transfers data in single bytes. this dma mode is configured by setting dmamode (dtctr register bit 6) to zero, and dma (dtctr register bit 5) to one. data flow direction and byte counts are configured the same as atapi dma modes of data transfer, but with command information being received via the ncr scsi controller registers external to the SAA7391 operation. the data transfer takes place as long as the dma request signal dmarq is true. the dmack signal is toggled by the host interface for each byte transferred as shown in fig.5. 7.5.13 b urst dma mode using multiplexed bus configuration in this mode the dma data is available on the dma bus when both, dbrd or dbwr and dmack are true. dmack remains asserted throughout the transfer while dbrd toggles for each transfer as shown in fig.6. to configure the host interface the dma mode and dma bits (dtctr bits 6 and 5) should be set to logic 1. fig.5 generic interface normal dma mode. handbook, full pagewidth mgk514 dmarq dmack dbrd/ dbwr
1997 aug 01 54 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.6 burst dma mode using multiplexed bus configuration. handbook, full pagewidth mgk515 dmarq dmack dbrd/ dbwr 7.6 microcontroller interface this section provides a brief introduction to the software and hardware environment expected in a system using the SAA7391 device. because all of the SAA7391 registers are randomly accessible, the processor controlling the SAA7391 is able to use interrupts. 7.6.1 k ernel based firmware it is recommended that the sub-cpu runs a multi-tasking kernel to properly support the multiple threads of operation that are required of it in use. therefore the memory mapper specified in this document has the concept of having 2 pages of memory for data. then one page of data space can be switched in to the memory map for each thread as needed, while still keeping a fixed part of the memory map for the interrupt service routines and other fixed housekeeping code and data. 7.6.2 16- bit registers automatic read and write all of the 16-bit registers provided in the SAA7391, are used by writing the most significant bit (msb) first. these registers are located in the address range ff20h to ff6fh together with some 8-bit registers. to facilitate snapshot reading or writing of the 16-bit register an 8-bit holding register is provided to store the spare byte of data. this is implemented in such a way that a 16-bit read consists of a sample of the value of the register at the instant that the high byte was read from that register. the low byte is kept in a holding register and presented to the sub-cpu when the low byte is requested. even if the sub-cpu is interrupted (and the holding register is then stacked and replaced during the service routine) the 16-bit read will be the value of the register at a single instance in time. similarly for writing, the high byte is held in the holding register to be written later to the 16-bit register at the same time as the low byte is written to the SAA7391. again the holding register must be saved during an interrupt service routine (isr) if the isr itself is likely to cause any 16-bit reads or writes to take place. it should be noted that any isr, which requires access to a 16-bit or 8-bit register in the address range ff20h to ff6fh, will overwrite the holding register and therefore its contents must be stacked before the interrupt is serviced. furthermore, there is only one holding register that may be accessed both for reading and writing. in this way the interrupt routine can easily save data that was stored in the holding register before it was written. a single location (temp_data, register ff6fh) is used as the location to read the value of the holding register, regardless of which address was used in the original read or write process. the irs stacking process of the holding register is illustrated in fig.8.
1997 aug 01 55 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 this is intended for big-endian high byte then low byte accesses to 16-bit register space. fig.7 holding register used in 16-bit access via 8-bit bus. handbook, full pagewidth mgk509 16-bit register file d8 to d15 a1 to an q8 to q15 q0 to q7 d0 to d7 address bus data bus 0 1 mux 0 1 mux read 8-bit holding register (ff6f) a0 loaded when: (a0 = 0 and write) or (a0 = 0 and read) 8 8 8 fig.8 stacking 8-bit holding register during interrupt service. handbook, halfpage read/write high1 read/write low1 save register read/write high2 read/write low2 restore register mgk510 program flow interrupt
1997 aug 01 56 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.7 8051 cpu and memory management functions the 8051 cpu and memory management functions are as follows: device registers are memory mapped for faster direct access to the chip provides direct access from sub-cpu to buffer ram to support scratchpad accesses; this eliminates the need for extra ram chips in the system address space reserved for generic host interface control and status pass-through (it is shared with atapi register space; see section 7.5) interfaces to 8051 multiplexed address and data bus two dynamically controllable ram access modes allow trade-off between accessible scratchpad ram size and ram access time. 7.7.1 s ub -cpu bus access timing the fast and slow ram access timing diagrams are illustrated in figs 10 and 9. it should be noted that fast ram access is not recommended due to its negative effect on the ram bandwidth and the overall system performance. in the fast ram access mode all external accesses below c000 are expected to be program fetches. a dram access cycle is not begun. above c000, the ram cycle begins on the falling edge of ale hence the number of 8051 wait states can be reduced. this is not however recommended. the disadvantage is, that the ram access cycle is started regardless of whether it will be needed. this has the effect of aborting any other on-going use of the buffer memory and reducing the available bandwidth. consequently, the number of wait states on accessing ram must be greater. in return, more ram is accessible. in the slow ram access mode the ram access cycle starts on the falling edge of rd or wr, if psen is high, this being the first time in the 8051 external memory access cycle that it is possible to determine that an xdata access is in fact being made. this access mode has a lower impact on the buffer ram memory bandwidth as only accesses that are needed are made. the two modes are under control of a register bit, and it is possible to switch between them at any time. fig.9 slow ram access mode timing. handbook, full pagewidth mgk516 (3) (1) (2) (4) sub-cpu clock sub-cpu ale xda8 to xda15 xda0 to xda7, xda8 to xda15 latched xdd0 to xdd7 rd/wr (1) SAA7391 accesses ram and stops clock until complete. (2) rd low or wr low indicates access actually taking place. (3) 8051 microcontroller continues. (4) address decoded for possible access ram.
1997 aug 01 57 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.10 fast ram access mode timing. handbook, full pagewidth mgk517 (2) (1) sub-cpu clock sub-cpu ale xda8 to xda15 xda0 to xda7, xda8 to xda15 latched xdd0 to xdd7 rd/wr (1) address decoded in upper 16 kbytes indicates access to ram or SAA7391 registers, ram access begins, SAA7391 accesses ram, sto ps clock only if SAA7391 asserts rd or wr before access complete. (2) 8051 microcontroller continues. 7.7.2 b uffer memory organisation memory is mapped as a 12-bit block number and a 12-bit offset into that block. the block oriented memory structure permits the use of 16-bit pointers in software, minimising the overhead of accessing memory. the address can be found from the following equation: the sub-cpu sees the SAA7391 as a memory mapped peripheral, with control and status registers appearing in the highest 256 bytes of the external address space (pdata space). the phrase (pdata space) is meant to imply that the code will access registers most efficiently if the pdata (8051 port p2) pointer is set to point at the register space of the SAA7391. if the pdata space is better used as context switching space then it can be used for that purpose. all registers and ram are accessible in the xdata space at all times, the pdata is just a movable 256 byte window with faster access into xdata. address block_number 2560 offset + = the lowest 56 kbytes of the 8051 external address data space is mappable as two windows into the memory of 52 kbytes and 4 kbytes, on any user-specified 256 byte boundary within the ram. this is usable as scratchpad ram. the two pages permits the paging of process context information for use with a multi-tasking kernel, while still keeping some global variables. the next 7.5 kbytes is mapped as a window into memory starting at a user-specified block number. this is usable for accessing block data, subcode information, error corrector status and block headers. the 64 kbytes memory mapping is shown in fig.11.
1997 aug 01 58 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 in fast ram mode (see conf_8051 bit 7) the lower 48 kbytes of ram space is not accessible as it is reserved for external rom. fig.11 memory mapping of the SAA7391 registers into 64 kbytes sub-cpu address space. handbook, full pagewidth mgk511 subseg 2 7.5 kbits window into 3 cd-rom blocks base address is moved in terms of block number 4 kbits always accessible, base address movable in 256 byte pages top 4 kbits always visible bottom 48 kbits not usable in fast ram mode subseg 1 subseg 0 subpage 2 subpage 1 0xff00 0xe000 0xd000 0xc000 0x0000 table 88 the SAA7391 memory map notes 1. if the SAA7391 is addressed in this area it will not access the dram and the data output of the sub-cpu interface to the microcontroller is disabled. if the SAA7391 host interface has been configured for generic mode and the address access from ffc0h to ffdfh, a chip select signal is asserted zero on the output pin xda1. 2. cpu address (bits 23 to 8) = 0. cpu address (bits 7 to 0) = address (bits 7 to 0). 3. read in this segment is always from internal the SAA7391 registers. write is to internal the SAA7391 registers and, optionally, also to dram if debug is set (conf_8051, bit 1 = 1). 4. cpu address (bits 8 to 0) = address (bits 8 to 0). cpu address (bits 23 to 9) = subseg 1 (bits 12 to 0) + subseg 1 (12 to 0) 4 + address (bits 12 to 9). 5. cpu address (bits 9 to 0) = address (bits 9 to 0). cpu address (bits 23 to 10) = subseg 2 (bits 15 to 2) + address (bits 11 and 10). 6. cpu address (bits 9 to 0) = address (bits 9 to 0). cpu address (bits 23 to 10) = subseg 1 (bits 15 to 2) + address (bits 15 to 10). address segment size (bytes) used for address function ffcoh to ffffh 64 the SAA7391s dead space none; note 1 ff00h to ffbfh 192 the SAA7391 register access, debug write to dram none; notes 2 and 3 e000h to feffh 7936 segments in dram note 4 d000h to dfffh 4096 subpage 2 in dram note 5 c000h to cfffh 4096 subpage 1 in dram note 6 0000h to bfffh 49152 subpage 1 in dram notes 1 and 6
1997 aug 01 59 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.7.3 s ubpage the lowest 52 kbytes (0x000h to 0xcfffh) of the external data memory is mapped to subpage1. if the user requires less ram than is provided here (up to 52 kbytes), the 1024 byte granularity of positioning the offsets permits the pages to be overlapped. in the fast ram access mode, the lowest 48 kbytes are not accessible as they are assumed to be rom space. the next 4 kbytes (0xd000h to 0xdfffh) of the external data memory is always mapped to subpage2, and is always available. table 89 subpage ram offsets 7.7.3.1 sub-cpu segment page the sub-cpu may access three adjacent segments of data offset from the base segment pointed to by subseg. these are mapped as a contiguous 7.5 kbytes block at the top of memory from 0xe000 to 0xf800. the buffer address is formed using the following equation: this permits the writing of headers and looking at subcode information which may span more than one segment. linked lists in the spare space at the end of a segment may be more easily manipulated if the segment and its neighbours are visible to the sub-cpu in a consistent manner. it is also possible to indirectly access any part of ram by using the block copy registers to move the data to and from the sub-cpu subpages. 7.7.3.2 sub-cpu segment page restriction it should be noted that the SAA7391 device does not have the concept of a defined upper limit on the segment addressed block. hence the segment page is always 3 contiguous segments of ram, even when near or at the top of accessible ram or at the top of the firmware defined data input buffer. in this case 1 or 2 of the blocks accessed will be beyond the buffer. table 90 sub-cpu segment ram offsets 7.8 external memory interface the external memory interface is designed to operate with up to 128 mbits hyper-page 33 mhz dram (edo ram) it is also designed to operate with fast-page dram giving a 17.5 mbyte/s burst transfer rate. figures 13 and 14 illustrate the timing diagram for fast-page mode. it should be noted that during the power-on reset cycle it is necessary to pull the xdata bus to all zeros to configure the SAA7391 for use with the 8051 microcontroller. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff18h subpage1-h a23 a22 a21 a20 a19 a18 a17 a16 ff19h subpage1-l a15 a14 a13 a12 a11 a10 - - ff1ah subpage2-h a23 a22 a21 a20 a19 a18 a17 a16 ff1bh subpage2-l a15 a14 a13 a12 - a10 - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff1ch subseg-h s7 s6 s5 s4 s3 s2 s1 s0 ff1dh subseg-l - - - - s11 s10 s9 s8 buffer address subseg down to 0 () 2560 sub-cpu (a12 down to 0) + =
1997 aug 01 60 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.8.1 dram interface configuration register table 91 dram_config: address ff6ah (see table 92) table 92 description of the dram interface features access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w - - - feature 4 feature 3 feature 2 feature 1 feature 0 feature 4 feature 3 feature 2 feature 1 feature 0 option 0xxxx refresh every 256 system clock cycles 1xxxx refresh every 511 system clock cycles x 1 x x x minimum ras low is 2 clock cycles x 0 x x x minimum ras low is 3 clock cycles x x 1 0 x 1 mbit 4 dram used x x 1 1 x 4 mbit 4 dram used x x 0 x x 512 kbits 8, 1 mbit 8, 2 mbits 8, 4 mbits 8, 8 mbits 8 or 16 mbits 8 dram used xxxx0 use fast-page mode device xxxx1 use hyper-page mode device 7.9 uart for communication with cd engine the following are required for communication with the cd engine: clock prescaler for selectable baud rate synchronous slave peripheral interface asynchronous uart dma to reduce sub-cpu loading in spi mode interrupt options available. 7.9.1 uart basic engine interface the basic engine interface implements both a synchronous peripheral interface and an asynchronous high-speed serial interface. the same registers are shared between the functions involved. transmitted and received data in asynchronous mode is sent or received with parity bits in 8-bit, one parity bit, one stop bit format. the registers that are implemented are described below. two 16-bit dma pointers (spi_rx_off and spi_tx_off) are provided so that the interface may be used in a dma mode. as a byte is transferred to or from the uart registers, it is possible to copy it into a part of the auxseg ram (16-bit register auxsegment-h or auxsegment-l) in the SAA7391s buffer memory. the pointers auto-increment and wrap within the region assigned, so if the user wishes the data to appear in the same place in the buffer for each dma transfer it will be necessary to reload these pointers before re-enabling dma for the data transfer. dma operation can be independently on for the transmit and receive channels. to enable the dma receive channel the uart_dma_ctrl bit 7 must be set to logic 1. when the receive dma channel is active the sub-cpu cannot read the receive register (rxdata address ff77h) any more but the SAA7391 will automatically copy the contents of the rxdata register to the address pointed at by the spi_rx_offset pointer if it is full, increment the spi_rx_offset pointer and reset the rvbfull bit. the spi offset registers are available in both synchronous and asynchronous modes and not just for spi. the spi_rx_offset register may be read to determine how many bytes have been received. the polarity of the spi clock is selectable from the uartcom register (see table 94). to enable the dma transmit channel the uart_dma_ctrl bit 6 must be set to logic 1 and, at the same time, bits 5 to 0 (txdmacount) must be greater than zero. when the transmit channel is active the sub-cpu can write to the transmit register (txdata address ff77h), however, the SAA7391 will automatically perform the following operation.
1997 aug 01 61 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 if (transmit register empty) end if; transmission will automatically stop when the uart_dma_ctrl (bits 5 to 0) (the txdmacount) has incremented to zero. this condi tion will produce the interrupt. data transmission rates are selectable by writing a value n(0 to 255) to the uart_pre_scaler register. the baud rate for each mod e can then be calculated as follows: for the spi mode for the s2b mode table 93 uart general registers notes 1. see table 95. 2. see table 96. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff28h auxsegment-h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ff29h auxsegment-l bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff4ah spi_rx_off-h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ff4bh spi_rx_off-l bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff4ch spi_tx_off-h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ff4dh spi_tx_off-l bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff74h uart_pre_scaler (rw)7 prescale value (bits 7 to 0) ff75h uart_dma_ctrl (rw) rcvdma on txdma on txdmacount (bits 5 to 0) ff76h uartcom (w) paron spion - - - - - parpol clkpol ff77h rxdata (w) d7 d6 d5 d4 d3 d2 d1 d0 ff7h rxdata (r) d7 d6 d5 d4 d3 d2 d1 d0 ff78h uarttintstat/reset (rw) comsync syssync not comsync not syssync not txbfull rvbfull overrun rvparity ff79h uarttinten (w) comsyn syssync not comsync not syssync not txbfull rvbfull overrun rvparity ff7eh uartstat (r) (1) comsync syssync comsync syssync txbfull rxbfull overrun rxparity ff7fh uartauxstat (r) (2) comiack txfull rxfull - - - - - transmitreg ram [auxsegment 2560 spi_tx _offset] + = spi_tx_offset spi_tx_offset 1 + = uart_dma_ctrl (5 : 0) uart_dma_ctrl (5 : 0) 1 C = f spi f sysclk 2n1 + () [] ----------------------------------- - = f s2b f sysclk 16 n 1 + () [] --------------------------------------- =
1997 aug 01 62 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 94 description of the uartcom register bits table 95 description of the uartstat register bits table 96 description of the uartauxstat register bits table 97 cd playback error rate measurement registers bit name value description 7 paron 0 disable parity bit in s2b mode 1 enable parity bit in s2b mode 6 spion 0 s2b transmission mode 1 spi transmission mode 0 parpol clkpol 0 spi clock active low; s2b even parity 1 spi clock active high; s2b odd parity bit name value description 7 comsync 0 comsync pin level 1 6 syssync 0 syssync pin level 1 5 comsync 0 inverted comsync pin level 1 4 syssync 0 inverted syssync pin level 1 3 txbfull 0 - 1 transmit data buffer is empty and ready for another byte 2 rxbfull 0 receive data buffer is not valid 1 receive data buffer is valid 1 overrun 0 - 1 a byte was lost because the rxdata register was not read in time 0 rxparity 0 - 1 received parity bit is in error bit name value description 7 comiack 0 comiack pin level 1 6 txfull 0 - 1 transmit register is full (a byte is being sent) 5 rxfull 0 - 1 receive register holds a byte, need to read a byte immediately to avoid overrun address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff11h c1blercnt d7 d6 d5 d4 d3 d2 d1 d0 ff12h c2blercnt d7 d6 d5 d4 d3 d2 d1 d0
1997 aug 01 63 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.10 clock generation control 7.10.1 c rystal oscillator the crystal oscillator is a conventional 2-pin inverting design operating from 8 to 35 mhz; this oscillator is also capable of operating with a 33.8 mhz ceramic resonator. it is capable of oscillating with both fundamental and 3rd-overtone mode crystals. external components should be used to suppress the fundamental output of the 3rd-overtone types as shown in fig.12. when operating with lower frequency crystals, r s must be greater than 0 w to avoid overdriving the crystal. fig.12 clock oscillator application circuit for 3rd-overtone crystal. handbook, halfpage mgk512 crout crin SAA7391 oscillator r s (0 w ) 100 k w 3.3 m h 1 nf 10 pf 10 pf 34 mhz
1997 aug 01 64 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7.10.2 s ub -cpu clock control register this register controls the clocking of the sub-cpu and the generation of wait states, ensuring a low jitter in the clock while allowing wait states. table 98 conf_8051: address ff73h (see table 99) table 99 description of the conf_8051 register bits note 1. the clock pulse provided to the 8051 is equal to the high period of sysclk for divide-by-1 and divide-by-1.5. for all other division ratios the clock pulse high time is equal to one cycle of sysclk. 7.10.3 SAA7391 system clock control registers table 100 clk_con register note 1. write operations to bit 6 of clk_con register may become unreliable once this bit has been written to with a logic 1. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 modsel wait2 wait1 wait0 div2 div1 div0 debug bit name value description 7 modsel 0 wait state control 1 6 to 4 wait2 to wait0 000 0 wait states 001 1 wait state 010 2 wait states 011 3 wait states 100 4 wait states 101 5 wait states 110 6 wait states 111 7 wait states 3 to 1 div2 to div0 000 8051 clock is sysclk; note 1 001 8051 clock is sysclk/1.5; note 1 010 8051 clock is sysclk/2 011 8051 clock is sysclk/3 100 8051 clock is sysclk/4 1xx unde?ned 0 debug 0 - 1 register writes are shadowed through into buffer ram address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ff9eh multi_con mode m6 m5 m4 m3 m2 m1 m0 ff9fh clk_con (1) pllpwr pllena ---- xtal1 xtal0
1997 aug 01 65 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 101 description of the clk_con register bits bit name value description f pll (khz) notes 7 pllpwr 0 pll is powered-down - default 1 pll is powered-up -- 6 pllena 0 system clock source is crin - default 1 system clock source is from clock multiplier -- 1 and 0 xtal1 and xtal0 00 crystal is 8.4672 mhz; divide-by-16 529.2 - 01 crystal is 11.289 mh; divide-by-22 513.1 - 10 crystal is 16.9344 mhz; divide-by-32 529.2 default 11 crystal is 33.8688 mhz; divide-by-64 529.2 - table 102 the relationship between the values of the m bits and vco frequency for a normalised pll frequency of 500 khz; note 1 m6 to m0 (hex) frequency (mhz) 02 3 04 4 08 5 11 6 22 7 44 8 09 9 13 10 26 11 4c 12 18 13 31 14 62 15 45 16 0b 17 17 18 2e 19 5d 20 3a 21 75 22 6b 23 56 24 2d 25 5b 26 36 27 6c 28 58 29 30 30 60 31 41 32 03 33 06 34 0c 35 19 36 33 37 66 38 4d 39 1a 40 35 41 6a 42 54 43 29 44 53 45 27 46 4e 47 1c 48 39 49 73 50 67 51 4f 52 1e 53 3d 54 m6 to m0 (hex) frequency (mhz)
1997 aug 01 66 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 7b 55 76 56 6d 57 5a 58 34 59 68 60 50 61 21 62 42 63 05 64 0a 65 15 66 2a 67 55 68 2b 69 57 70 2f 71 5f 72 3e 73 7d 74 7a 75 74 76 69 77 52 78 25 79 4a 80 14 81 28 82 51 83 23 84 46 85 0d 86 1b 87 37 88 6e 89 5c 90 38 91 71 92 63 93 47 94 m6 to m0 (hex) frequency (mhz) note 1. it should be noted that the mode bit (msb high byte) has not been included in the table. the oscillator output frequency can be determined by dividing the vco frequency given in table 102 according to the mode bit described in table 103. 0f 95 1f 96 3f 97 7f 98 7e 99 7c 100 78 101 70 102 61 103 43 104 07 105 0e 106 1d 107 3b 108 77 109 6f 110 5e 111 3c 112 79 113 72 114 65 115 4b 116 16 117 2c 118 59 119 32 120 64 121 49 122 12 123 24 124 48 125 10 126 20 127 40 128 m6 to m0 (hex) frequency (mhz)
1997 aug 01 67 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 103 explanation of mode bit 8 limiting values in accordance with the absolute maximum rating system (iec 134) 9 thermal characteristics 10 characteristics mode bit division ratio 0 divide the frequency from table 102 by 4 to obtain sysclk frequency 1 divide the frequency from table 102 by 2 to obtain sysclk frequency symbol parameter min. typ. unit v ddd(core) core digital supply voltage - 0.5 +4.5 v v ddd(pad) periphery digital supply voltage - 0.5 +6.5 v v dda analog supply voltage - 0.5 +4.6 v v i(max) maximum voltage on any input - 0.5 v ddd(pad) + 0.5 v v o output voltage on any output - 0.5 +6.5 v i o output current (continuous) - 20 ma p power dissipation - 400 mw t stg storage temperature - 55 +125 c t amb operating ambient temperature 0 70 c symbol parameter conditions value unit r thj-a thermal resistance from junction to ambient in free air 55 k/w symbol parameter conditions min. typ. max. unit digital inputs i nputs designated by c (cmos voltage levels ) v il low-level input voltage - 0.3 - 0.3v ddd(pad) v v ih high-level input voltage 0.7v ddd(pad) - v ddd(pad) + 0.3 v i li input leakage current v i = 0 to v ddd(pad) - 10 - 10 m a c i input capacitance - - 10 pf i nputs designated by t (ttl voltage levels ) v il low-level input voltage - 0.3 - 0.8 v v ih high-level input voltage 2.0 - v ddd(pad) + 0.3 v i li input leakage current v i = 0 to v ddd(pad) - 10 - 10 m a c i input capacitance - - 10 pf
1997 aug 01 68 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 por and reset ( schmitt trigger ) v th(pos) schmitt trigger positive-going switching threshold voltage - - 0.8v ddd(pad) v v th(neg) schmitt trigger negative-going switching threshold voltage 0.2v ddd(pad) - - v v hys hysteresis voltage 1.0 - - v c i input capacitance - - 3 pf digital outputs o utputs designated by l (cmos levels ) v ol low-level output voltage i ol =2ma 0 - 0.4 v v oh high-level output voltage i oh = - 2ma v ddd(pad) - 0.4 - v ddd v c l load capacitance - - 20 pf t o(r) output rise time c l = 20 pf; 10% to 90% - - 10 ns t o(f) output fall time c l = 20 pf; 90% to 10% - - 10 ns o utputs designated by m (cmos levels ) v ol low-level output voltage i ol =4ma 0 - 0.4 v v oh high-level output voltage i oh = - 4ma v ddd(pad) - 0.4 - v ddd v c l load capacitance - - 20 pf t o(r) output rise time c l = 20 pf; 10% to 90% - - 8 ns t o(f) output fall time c l = 20 pf; 90% to 10% - - 8 ns o utputs designated by h (cmos levels ) v ol low-level output voltage i ol =8ma 0 - 0.4 v v oh high-level output voltage i oh = - 8ma v ddd(pad) - 0.4 - v ddd v c l load capacitance - - 20 pf t o(r) output rise time c l = 20 pf; 10% to 90% - - 6 ns t o(f) output fall time c l = 20 pf; 90% to 10% - - 6 ns o utputs : designated by al (ata data bus levels ) v ol low-level output voltage i ol =4ma 0 - 0.4 v v oh high-level output voltage i oh = - 4ma 2.4 - v ddd v c l load capacitance - - 100 pf t o(r) output rise time c l = 40 pf; 10% to 90% 5 - - ns t o(f) output fall time c l = 40 pf; 90% to 10% 5 - - ns symbol parameter conditions min. typ. max. unit
1997 aug 01 69 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 o utputs : designated by ah (ata levels ) v ol low-level output voltage i ol =12ma 0 - 0.4 v v oh high-level output voltage i oh = - 4ma 2.4 - v ddd v c l load capacitance - - 100 pf t o(r) output rise time c l = 40 pf; 10% to 90% 5 - - ns t o(f) output fall time c l = 40 pf; 90% to 10% 5 - - ns crystal oscillator input: crin f clk external clock frequency 8 8.4677 35 mhz v il low-level input voltage - 0.3 - 0.3v ddd(core) v v ih high-level input voltage 0.7v ddd(core) - v ddd(c) + 0.3 v i li input leakage current - 10 - 10 m a c i input capacitance - - 10 pf crystal oscillator output: crout f xtal crystal frequency - - 35 mhz gm transconductance 16 - - m s r o output resistance - - - g v small signal voltage gain g v =gm r o 5 - - v/v c fb feedback capacitance - - 5 pf c o output capacitance - - 10 pf symbol parameter conditions min. typ. max. unit
1997 aug 01 70 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 11 timing characteristics 11.1 external memory interface timing table 104 dram interface timing (fast-page mode); see figs 13 and 14 and note 1 note 1. for further information regarding the dram timing please consult the device user manual or contact product support. symbol parameter conditions min. max. unit t cy read or write cycle period 160 - ns t acc(cas) access time from cas - 20 ns t acc(ras) access time from ras -- ns t rash ras high time 70 - ns t rasl ras low time 80 10000 ns t h(ras) ras hold time 20 - ns t casl cas low time 20 10000 ns t h(cas) cas hold time 80 - ns t d(cash-ras) delay time cas high to ras 10 - ns t d(ras-cas) ras to cas delay time 25 - ns t d(ras-ca) ras to column address delay time 20 - ns t su(ra) row address set-up time 0 - ns t h(ra) row address hold time 15 - ns t su(ca) column address set-up time 0 - ns t h(ca) column address hold time 20 - ns t h(ca-rasl) column address hold time from ras low 60 - ns t l(ca-ras) column address to ras lead time 40 - ns t h(r) read command hold time 0 - ns t h(r-ras) read command hold time from ras 60 - ns t su(w) write command set-up time 0 - ns t h(w) write command hold time 15 - ns t wl write command low time 15 - ns t h(w-ras) write command hold time from ras 60 - ns t l(w-cas) write command to cas lead time 20 - ns t l(w-ras) write command to ras lead time 20 - ns t su(do) data output set-up time 0 - ns t h(do) data output hold time 15 - ns t h(do-ras) data output hold time from ras 60 - ns
1997 aug 01 71 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.13 external dram write cycle timing for fast-page. handbook, full pagewidth mgk518 xda0 to xda13 xdd0 to xdd7 xras xcas xwr row column t cy t rash t rasl t h(ras) t h(cas) t d(cash-ras) t d(cash-ras) t d(ras-cas) t d(ras-ca) t su(ra) t h(ra) t su(ca) t h(ca) t su(w) t h(w) t su(do) t h(do) t h(do-ras) t wl t h(ca-rasl) t h(w-ras) t l(w-cas) t l(w-ras) t l(ca-ras) t casl
1997 aug 01 72 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.14 external dram read cycle timing for fast-page. handbook, full pagewidth mgk519 input xda0 to xda13 xdd0 to xdd7 xras xcas xwr row column t cy t rash t rasl t h(ras) t h(cas) t d(cash-ras) t d(cash-ras) t d(ras-cas) t d(ras-ca) t su(ra) t h(ra) t su(ca) t h(ca) t h(r) t acc(ras) t acc(cas) t h(ca-rasl) t h(r-ras) t l(ca-ras) t casl
1997 aug 01 73 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 11.2 host interface timing this section deals with the implemented timings of the SAA7391 host interface in both the atapi and generic interface modes. the timings of the atapi pio mode 3 and mode 4 are also taken into account. table 105 basic ac characteristics, ata bus 11.2.1 h ost interface atapi pio and dma timing this section deals with the implemented timings of the SAA7391 host interface in both the atapi and generic interface modes. the timings of the atapi pio mode 3 and mode 4 are also taken into account (see table 105). symbol parameter conditions min. max. unit t r rise time for any signal on atapi interface 10 to 90% of full signal amplitude with a total capacitive load of 100 pf 5 - ns t f fall time for any signal on atapi interface 10 to 90% of full signal amplitude with a total capacitive load of 100 pf 5 - ns c i input capacitance for each host or device - 25 pf c o output capacitance for each host or device - 25 pf
1997 aug 01 74 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 11.2.2 ata bus timing the figures and timing characteristics detail the timing as specified in the ata-3 documentation. table 106 timing of pio data transfer to and from device; see fig.15 symbol parameter conditions min. max. unit t cy cycle time note 1 mode 0 600 - ns mode 1 383 - ns mode 2 240 - ns mode 3 180 - ns mode 4 120 - ns t su(a-dior/diow) address valid to dior/ diow set-up time mode 0 70 - ns mode 1 50 - ns mode 2 30 - ns mode 3 30 - ns mode 4 25 - ns t w(dior/diow) dior/ diow pulse width 16-bit; note 1 mode 0 165 - ns mode 1 125 - ns mode 2 100 - ns mode 3 80 - ns mode 4 70 - ns 8-bit; note 1 mode 0 290 - ns mode 1 290 - ns mode 2 290 - ns mode 3 80 - ns mode 4 70 - ns t rec(dior/diow) dior/ diow recovery time note 1 mode 0 -- ns mode 1 -- ns mode 2 -- ns mode 3 70 - ns mode 4 25 - ns t su(diow) diow data set-up time mode 0 60 - ns mode 1 45 - ns mode 2 30 - ns mode 3 30 - ns mode 4 20 - ns
1997 aug 01 75 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 t h(diow) diow data hold time mode 0 30 - ns mode 1 20 - ns mode 2 15 - ns mode 3 10 - ns mode 4 10 - ns t su(dior) dior data set-up time mode 0 50 - ns mode 1 35 - ns mode 2 20 - ns mode 3 20 - ns mode 4 20 - ns t h(dior) dior data hold time mode 0 5 - ns mode 1 5 - ns mode 2 5 - ns mode 3 5 - ns mode 4 5 - ns t z(dior) dior data 3-state note 2 mode 0 - 30 ns mode 1 - 30 ns mode 2 - 30 ns mode 3 - 30 ns mode 4 - 30 ns t ass(a-iocs16) address valid to iocs16 assertion time note 3 mode 0 - 90 ns mode 1 - 50 ns mode 2 - 40 ns mode 3 -- ns mode 4 -- ns t rel(a-iocs16) address valid to iocs16 released time note 3 mode 0 - 60 ns mode 1 - 45 ns mode 2 - 30 ns mode 3 -- ns mode 4 -- ns t h(dior/diow-a) dior/ diow to address valid hold time mode 0 20 - ns mode 1 15 - ns mode 2 10 - ns mode 3 10 - ns mode 4 10 - ns symbol parameter conditions min. max. unit
1997 aug 01 76 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 notes 1. t cy is the minimum total cycle time, t w(dior/diow) is the minimum command active time, and t rec(dior/diow) is the minimum command recovery time or command inactive time. the actual cycle time equals the sum of the actual command active time and the actual command inactive time. the three timing requirements of t cy , t w(dior/diow) , and t rec(dior/diow) shall be met. the minimum total cycle time requirements is greater than the sum of t w(dior/diow) and t rec(dior/diow) . this means a host implementation can lengthen either or both t w(dior/diow) or t rec(dior/diow) to ensure that t cy is equal to or greater than the value reported in the devices identify drive data. a device implementation shall support any legal host implementation. 2. this parameter specifies the time from the negation edge of dior to the time that the data bus is no longer driven by the device (3-state). 3. the delay from the activation of dior or diow until the state of iordy is first sampled. if iordy is inactive then the host shall wait until iordy is active before the pio cycle can be completed. if the device is not driving iordy negated at the t su(iordy) after the activation of dior or diow, then t su(dior) shall be met and t r(dat-iordy) is not applicable. if the device is driving iordy negated at the time t su(iordy) after the activation of dior or diow, then t r(dat-iordy) shall be met and t su(dior) is not applicable. 4. t ass(a-iocs16) and t rel(a-iocs16) apply only to modes 0, 1 and 2. this signal is not valid for other modes. t r(dat-iordy) read data valid to iordy active (if iordy initially low after t su(iordy) ) mode 0 0 - ns mode 1 0 - ns mode 2 0 - ns mode 3 0 - ns mode 4 0 - ns t su(iordy) iordy set-up time note 4 mode 0 35 - ns mode 1 35 - ns mode 2 35 - ns mode 3 35 - ns mode 4 35 - ns t w(iordy) iordy pulse width mode 0 - 1250 ns mode 1 - 1250 ns mode 2 - 1250 ns mode 3 - 1250 ns mode 4 - 1250 ns symbol parameter conditions min. max. unit
1997 aug 01 77 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.15 ata bus timing diagram. handbook, full pagewidth mgk520 address valid dior/diow read dd0 to dd15 iocs16 iordy no wait iordy ignoring glitch iordy causing wait write dd0 to dd15 t cy t su(a-dior/diow) t h(dior/diow-a) t r(dat-iordy) t su(iordy) t w(iordy) t w(a-dior/diow) t rec(a-dior/diow) t ass(a-iocs16) t rel(a-iocs16) t su(diow) t h(diow) t su(dior) t h(dior) t z(dior)
1997 aug 01 78 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 107 single word dma timing; see fig.16 symbol parameter conditions min. max. unit t cy cycle time mode 0 960 - ns mode 1 480 - ns mode 2 240 - ns t d(dmack-dmarq) dmack to dmarq delay mode 0 - 200 ns mode 1 - 100 ns mode 2 - 80 ns t w(dior/diow) dior/ diow pulse width 16-bit mode 0 480 - ns mode 1 240 - ns mode 2 120 - ns t acc(dior) dior data access time mode 0 - 250 ns mode 1 - 150 ns mode 2 - 60 ns t h(dior) dior data hold time mode 0 5 - ns mode 1 5 - ns mode 2 5 - ns t su(diow) diow data set-up time mode 0 250 - ns mode 1 100 - ns mode 2 35 - ns t h(diow) diow data hold time mode 0 50 - ns mode 1 30 - ns mode 2 20 - ns t su(dmack-dior/diow) dmack to dior/ diow set-up time mode 0 0 - ns mode 1 0 - ns mode 2 0 - ns t h(dior/diow-dmack) dior/ diow to dmack hold time mode 0 0 - ns mode 1 0 - ns mode 2 0 - ns t su(dior) dior set-up time mode 0 t w(dior/diow) - t acc(dior) - ns mode 1 t w(dior/diow) - t acc(dior) - ns mode 2 t w(dior/diow) - t acc(dior) - ns
1997 aug 01 79 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.16 ata single word dma timing. handbook, full pagewidth mgk521 dmarq dmack dior/diow read dd0 to dd15 write dd0 to dd15 t cy t w(dior/diow) t acc(dior) t su(diow) t su(dior) t h(diow) t h(dior) t su(dmack-dior/diow) t h(dior/diow-dmack) t d(dmack-dmarq)
1997 aug 01 80 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 table 108 multi-word dma timing; see fig.17 symbol parameter conditions min. max. unit t cy cycle time note 1 mode 0 480 - ns mode 1 150 - ns mode 2 120 - ns t w(dior/diow) dior/ diow pulse width 16-bit mode 0 215 - ns mode 1 80 - ns mode 2 70 - ns t acc(dior) dior data access time mode 0 - 150 ns mode 1 - 60 ns mode 2 -- ns t h(dior) dior data hold time note 2 mode 0 5 - ns mode 1 5 - ns mode 2 5 - ns t su(diow) diow data set-up time mode 0 100 - ns mode 1 30 - ns mode 2 20 - ns t h(diow) diow data hold time mode 0 20 - ns mode 1 15 - ns mode 2 10 - ns t su(dmack-dior/diow) dmack to dior/ diow set-up time mode 0 0 - ns mode 1 0 - ns mode 2 0 - ns t h(dior/diow-dmack) dior/ diow to dmack hold time mode 0 20 - ns mode 1 5 - ns mode 2 5 - ns t wneg(dior) dior negated pulse width note 1 mode 0 50 - ns mode 1 50 - ns mode 2 25 - ns t wneg(diow) diow negated pulse width note 1 mode 0 215 - ns mode 1 50 - ns mode 2 25 - ns t d(dior-dmarq) delay time from dior to dmarq mode 0 - 120 ns mode 1 - 40 ns mode 2 - 35 ns t d(diow-dmarq) delay time from diow to dmarq mode 0 - 40 ns mode 1 - 40 ns mode 2 - 35 ns
1997 aug 01 81 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 notes 1. t cy is the minimum total cycle time, t w(dior/diow) is the minimum command active time, and t wneg(dior) or t wneg(diow) , as appropriate) is the minimum command recovery time or command inactive time. the actual cycle time equals the sum of the actual command active time and the actual command inactive time. the three timing requirements of t cy , t w(dior/diow) and t wneg(dior) or t wneg(diow) shall be met. the minimum total cycle time requirement, t cy , is greater than the sum of t w(dior/diow) and t wneg(dior) or t wneg(diow) . this means a host implementation can lengthen either or both t w(dior/diow) or t wneg(dior) or t wneg(diow) to ensure that t cy is equal to the value reported in the devices identify drive data. a device implementation shall support any legal host implementation. 2. the original ata standard defined a maximum value for t h(dior) . the meaning of this value was not clear. this parameter has been renamed to t d(dmack-z) and specifies the time from the negation edge of dmack to the time the device data signals are no longer driven by the device (3-state). the t d(dmack-z) parameter applies only at the end of a multi-word dma cycle, i.e., when dmack is negated. the device may actively drive the device data signals, or may 3-state the device data signals, while dmack is active from the first time that dior is asserted until dmack is negated as long as t acc(dior) and t h(dior) requirements are met. t d(dmack-z) delay time from dmack to 3-state note 2 mode 0 - 20 ns mode 1 - 25 ns mode 2 - 25 ns symbol parameter conditions min. max. unit
1997 aug 01 82 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.17 multi-word dma timing. (1) this signal may be negated by the host to suspend the dma transfer in progress. for multi-word dma transfers, the device may negate dmarq within the t d(dior-dmarq) or t d(diow-dmarq) specified time once dmack is asserted and reassert it again at a later time to resume the dma operation. alternatively, if the device is able to continue the transfer of data, the device may leave dmarq asserted and wait for the hos t to reassert dmack. handbook, full pagewidth mgk522 dmarq dmack dior/diow read dd0 to dd15 write dd0 to dd15 t cy t w(dior/diow) t wneg(dior) t wneg(diow) t su(diow) t h(diow) t acc(dior) t h(dior) t su(dmack-dior/diow) t d(dmack-z) t h(dior/diow-dmack) t d(dior-dmarq) (1)
1997 aug 01 83 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 11.2.3 u ltra dma operation and timing selection of ultra dma is similar to multi-word dma operation. bits 5, 6 and 7 of the dtctr register should all be set to logic 1 and data byte counts and data flow selection does not change from atapi dma operation. the ultra_stop interrupt (ifstat bit 4) when enabled by ultra_stopien (ifctrl bit 4) will interrupt the microcontroller if the host stops a transfer before the required data has been transfer i.e. the data byte count has not reached zero. a flag, crc_error (ifstat bit 0) if asserted in conjunction with the dtei interrupt (ifstat bit 6) will indicate to the microcontroller that the last transfer of data was corrupt. no changes of pin direction are required for ultra dma, but the ata description changes (see table 109). table 109 ultra dma pin changes 11.2.4 u ltra dma read / write timing this section provides the timing diagrams for the ultra dma protocol. the timing diagrams are shown in figs 18 to 27. the timing information is provided in table 110. table 110 timing parameter values; see figs 18 to 27 ata pin name ultra dma read pin name ultra dma write pin name comment iordy sender strobe d_dmardy (device dma ready) d_dmardy can be used to pause transmission dmarq dmarq dmarq similar to atapi dma dmack dmack dmack similar to atapi dma, but also used at the end of transmission for the crc strobe dior stop sender strobe stop can terminate the data transfer before all bytes have been transferred; this action will generate a microcontroller interrupt diow h_dmardy (host dma ready) stop h_dmardy can be used by to pause transmission symbol parameter conditions min. max. unit t cy cycle time (from strobe edge to strobe edge) mode 0 117 - ns mode 1 77 - ns mode 2 57 - ns t su(d)(rx) data set-up time (at receiver) mode 0 15 - ns mode 1 10 - ns mode 2 7 - ns t h(d)(rx) data hold time (at receiver) mode 0 3 - ns mode 1 3 - ns mode 2 3 - ns t su(dv) data valid set-up time (at sender); time from data bus being valid until strobe edge mode 0 75 - ns mode 1 48 - ns mode 2 38 - ns
1997 aug 01 84 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 t h(dv) data valid hold time (at sender); time from strobe edge until data goes invalid mode 0 8 - ns mode 1 8 - ns mode 2 8 - ns t li limited interlock time; time allowed between an action by one agent and the following action by the other agent mode 0 0 150 ns mode 1 0 150 ns mode 2 0 150 ns t li(min) limited interlock time with minimum mode 0 20 150 ns mode 1 20 150 ns mode 2 20 150 ns t ui unlimited interlock time mode 0 0 - ns mode 1 0 - ns mode 2 0 - ns t (o-z)(max) maximum time allowed for outputs to 3-state mode 0 - 10 ns mode 1 - 10 ns mode 2 - 10 ns t d(min) minimum delay time for output drivers turning on (from high-impedance) mode 0 20 - ns mode 1 20 - ns mode 2 20 - ns t env envelope time (all control signal transitions are within the dackb envelope by this time) mode 0 20 70 ns mode 1 20 70 ns mode 2 20 70 ns t res(strobe-dmardy) strobe-to-dmardy response time to ensure synchronous pause case (when receiver is pausing) mode 0 - 50 ns mode 1 - 30 ns mode 2 - 20 ns t (ready-strobe) ready-to-?nal-strobe time (this long after dmardyb de-assertion, no more strobe edges may be sent) mode 0 - 75 ns mode 1 - 60 ns mode 2 - 50 ns t (ready-pause) ready-to-pause time: time until a receiver may assume that the sender has paused after de-asserting dmardyb mode 0 160 - ns mode 1 125 - ns mode 2 100 - ns t pu pull-up time before allowing iordy to go high-impedance mode 0 - 20 ns mode 1 - 20 ns mode 2 - 20 ns t (iordy)(max) maximum time driver must wait before driving iordy mode 0 0 - ns mode 1 0 - ns mode 2 0 - ns t su(ass/deass) set-up time before assertion and de-assertion of dackb mode 0 20 - ns mode 1 20 - ns mode 2 20 - ns symbol parameter conditions min. max. unit
1997 aug 01 85 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 t h(ass/deass) hold time before assertion and de-assertion of dackb mode 0 20 - ns mode 1 20 - ns mode 2 20 - ns t ss(strobe-stop) time from strobe edge to negation of dmarq or assertion of stop mode 0 50 - ns mode 1 50 - ns mode 2 50 - ns symbol parameter conditions min. max. unit fig.18 sustained synchronous dma burst timing diagram. handbook, full pagewidth t cy t h(dv) t h(d)(rx) t su(d)(rx) t h(d)(rx) t su(d)(rx) t h(d)(rx) t h(dv) t su(dv) t su(dv) t cy t h(dv) strobe at sender data at sender strobe at receiver data at receiver mgk523 fig.19 host stop request (write command). handbook, halfpage mgk524 strobe (host) stop t ss(strobe-stop)
1997 aug 01 86 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.20 drive stop request (read command). handbook, halfpage mgk525 strobe (drive) drq t ss(strobe-stop) fig.21 drive initiating a dma burst for a write command. handbook, full pagewidth mgk526 dackb (host) drq (drive) stop (host) dmardy (host) strobe (drive) data (drive) da and cs t li t li t d(min) t su(dv) t h(dv) t ui t (o-z)(max) t env t env t (iordy)(max) t su(ass/deass) t su(ass/deass) t su(ass/deass)
1997 aug 01 87 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.22 receiver pausing a dma burst. handbook, full pagewidth mgk527 dackb (host) drq (drive) stop (host) dmardy (drive) strobe (host) data (host) da and cs t su(dv) t h(dv) t li t ui t ui t env t (iordy)(max) t h(ass/deass) t h(ass/deass)
1997 aug 01 88 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.23 receiver pausing a dma burst. handbook, full pagewidth mgk528 t (ready-pause) t (ready-pause) t res(strobe-dmardy) t (ready-strobe) dackb (host) drq (drive) stop (host) dmardyb strobe data
1997 aug 01 89 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.24 drive terminating a dma burst during a read command. handbook, full pagewidth mgk529 t li t li crc dackb (host) drq (drive) stop (host) dmardyb (host) strobe (drive) data (drive) da and cs t su(dv) t h(dv) t li t d(min) t (o-z)(max) t (iordy)(max) t su(ass/deass) t su(ass/deass) t su(ass/deass) t li(min)
1997 aug 01 90 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.25 drive terminating a dma burst during a write command. handbook, full pagewidth mgk530 dackb (host) drq (drive) stop (host) dmardyb (drive) strobe (host) data (host) da and cs crc t li t li t li(min) t li(min) t su(dv) t h(dv) t (iordy)(max) t su(ass/deass) t su(ass/deass) t su(ass/deass)
1997 aug 01 91 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.26 host terminating a dma burst during a read command. handbook, full pagewidth mgk531 drq (drive) dackb (host) stop (host) dmardyb (host) strobe (drive) data (drive) da and cs t h(dv) crc t li t li t li(min) t li(min) t su(dv) t (iordy)(max) t su(ass/deass) t su(ass/deass) t su(ass/deass) t (o-z)(max) t d(min)
1997 aug 01 92 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 11.3 sub-cpu interface timing table 111 timing parameter values for figs 28 and 29 note 1. t clcl = the SAA7391 system clock period. symbol parameter min. max. unit t avll address valid to ale low 10 - ns t rldv rd low to valid data in - 7t clcl +20 (1) ns t w(ale) ale pulse width 35 - ns t h(a) address hold time 10 - ns t dvwl data valid before wr low 0 - ns fig.27 host terminating a dma burst during a write command. handbook, full pagewidth mgk532 drq (drive) dackb (host) stop (host) dmardyb (drive) strobe (host) data (host) da and cs crc t li t li t li t li(min) t su(dv) t h(dv) t (iordy)(max) t su(ass/deass) t su(ass/deass) t su(ass/deass)
1997 aug 01 93 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 fig.28 timing diagram for an 8051 microcontroller interface read cycle. handbook, full pagewidth mgl165 ale port 0 port 2 a8 to a15 a0 to a7 data in a0 to a7 rd t rldv t w(ale) t h(a) fig.29 timing diagram for an 8051 microcontroller interface write cycle. handbook, full pagewidth mgl166 ale port 0 port 2 a8 to a15 a0 to a7 data out a0 to a7 wr t avll t dvwl
1997 aug 01 94 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 11.4 uart timing fig.30 timing diagram of byte transmission of uart in asynchronous mode. see section 7.9 for relevant timing. handbook, full pagewidth mgk614 0 idle 1 10 period (80 to 320 m s) 234567p stop next start may be here data parity start fig.31 timing diagram of spi mode, byte transmission of uart in synchronous mode. see section 7.9 for relevant timing. handbook, full pagewidth mgk615 bit 7 serin, serout spi clock rxfull 'erln' samples txfull spi ack bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1997 aug 01 95 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 12 appendix a table 112 the SAA7391 register map address name access block number of bits comment elm near equivalent register chaucer near equivalent register ff00h head0 r drive 8 see table 20 head0 - ff01h head1 r drive 8 head1 - ff02h head2 r - 8 head2 - ff03h head3 r - 8 head3 - ff04h subhead0 r - 8 shead0 - ff05h subhead1 r - 8 shead1 - ff06h subhead2 r - 8 shead2 - ff07h subhead3 r - 8 shead3 - ff08h stat0 r - 8stat0 - ff09h stat1 r - 8stat1 - ff0ah stat2 r - 8stat2 - ff0bh stat3 r - 8stat3 - ff0ch stat4 r - 8stat3 - ff0dh ctrl0 w - 8 see table 16 ctrl0 - ffoeh ctrl1 w - 8 ctrl1 - ff0fh ctrl2 w - 8 ctrl1 - ff10h ifconfig w drive 8 see table 12 ifconfig fectrl ff11h c1blercnt r - 8 see table 97 -- ff12h c2blercnt r - 8 -- ff13h submodetx w - 8 see table 30 -- ff14h mmaud w - 8 see table 35 -- ff15h mck_con w - 8 -- ff16h mmctrl w - 8 -- ff17h submoderx w - 8 see table 32 -- ff18h subpage1-h w - 16 see table 89 - pagereg ff19h subpage1-l w -- pagereg ff1ah subpage2-h w - 16 -- ff1bh subpage2-l w ---
1997 aug 01 96 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 ff1ch subseg1-h w - 16 see table 90 - micfrm# ff1dh subseg1-l w -- micfrm# ff1eh ------- ff1fh ------- ff20h drivecurseg-h rw - 16 see table 14 - fefrm# ff21h drivecurseg-l rw -- fefrm# ff22h driveprevseg-h rw - 16 - lastcmpfm/ec cfrm ff23h driveprevseg-l rw -- fefrmoff ff24h driveoffset-h rw - 16 - fefrmoff ff25h driveoffset-l rw --- ff26h drivenextseg-h rw - 16 see table 14 -- ff27h drivenextseg-l rw --- ff28h auxsegment-h rw - 16 see table 29 -- ff29h auxsegment-l rw --- ff2ah subpointr-h rw - 16 see table 34 -- ff2bh subpointr-l rw --- ff2ch subbasepointr-h rw - 16 -- ff2dh subbasepointr-l rw --- ff2eh subpointw-h rw - 16 sub-h - ff2fh subpointw-l rw - sub-l - ff30h subbasepointw-h rw - 16 sub-h - ff31h subbasepointw-l rw - sub-l - ff32h cdda-h rw - 16 see table 35 -- ff33h cdda-l rw --- ff34h daoffset-h rw - 16 -- ff35h daoffset-l rw --- address name access block number of bits comment elm near equivalent register chaucer near equivalent register
1997 aug 01 97 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 ff36h copyfromoffset-h rw - see table 42 - ff37h copyfromoffset-l rw --- ff38h copytooffset-h rw - 16 -- ff39h copytooffset-l rw --- ff3ah copyfromseg-h rw - 16 -- ff3bh copyfromseg-l rw --- ff3ch copytoseg-h rw --- ff3dh copytoseg-l rw --- ff3eh from2offset-h rw - 16 -- ff3fh from2offset-l rw --- ff40h to2offset-h rw - 16 -- ff41h to2offset-l rw --- ff42h hostbyteoffset-h rw - 16 see table 85 dac - ff43h hostbyteoffset-l rw - dac - ff44h hostcurseg-h rw - 16 dac scsicfrm ff45h hostcurseg-l rw - dac scsicfrm ff46h ------- ff47h ------- ff48h ------- ff49h ------- ff4ah spi_rx_off-h rw - 16 see table 93 -- ff4bh spi_rx_off-l rw --- ff4ch spi_tx_off-h rw - 16 -- ff4dh spi_tx_off-l rw --- ff4eh ------- ff4fh ------- address name access block number of bits comment elm near equivalent register chaucer near equivalent register
1997 aug 01 98 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 ff50h hostsubblkoffset2-h rw - 16 see table 85 -- ff51h hostsubblkoffset2-l rw --- ff52h hostsubblkcount2-h rw - 16 -- ff53h hostsubblkcount2-l rw --- ff54h hostnextseg-h rw - 16 - scsisfrm ff55h hostnextseg-l rw -- scsisfrm ff56h hostreloadflags rw - 16 -- ff57h hostnextsegcount rw --- ff58h hostsubblkoffset0-h rw - 16 -- ff59h hostsubblkoffset0-l rw --- ff5ah hostsubblkcount0-h rw - 16 -- ff5bh hostsubblkcount0-l rw --- ff5ch hostsubblkoffset1-h rw - 16 -- ff5dh hostsubblkoffset1-l rw --- ff5eh hostsubblkcount1-h rw - 16 -- ff5fh hostsubblkcount1-l rw --- ff60h drivecurcount rw - 8 see table 14 -- ff61h drivenextcount rw - 8 -- ff62h copycount-h rw - 8 see table 42 -- ff63h copycount-l rw - 8 -- ff64h hostbytecount-h rw - 8 see table 85 -- ff65h hostbytecount-l rw - 8 -- ff66h hostcursegcnt rw - 8 -- ff67h copycontrol rw - 8 see table 42 -- ff68h hostrelseg-h rw - 16 see table 85 -- ff69h hostrelseg-l rw --- ff6ah dram_config w - 8 see table 90 mems dramsel ff6bh aux_form_scan rw - 8 see table 85 -- ff6ch ------- ff6dh ------- address name access block number of bits comment elm near equivalent register chaucer near equivalent register
1997 aug 01 99 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 ff6eh ------- ff6fh temp_data rw - 8 holding register; see section 7.6 -- ff70h iecctrl w - 8 see table 35 -- ff71h ieccat w - 8 -- ff72h ------- ff73h conf_8051 w - 8 see table 98 -- ff74h uart_prescaler rw - 8 see table 93 -- ff75h uart_dma_ctrl rw - 8 - brgsel ff76h uartcom w - 8 -- ff77h rxdata/txdata rw - 8 - sercom ff78h uartintstat/reset rw - 8 -- ff79h uartintenable w - 8 -- ff7ah int1stat/reset rw - 8 see tables 45 and 46 -- ff7bh int1enable w - 8 see table 47 -- ff7ch int2stat/reset rw - 8 see tables 48 and 49 -- ff7dh int2enable w - 8 see table 50 -- ff7eh uartstat r - 8 see table 93 -- ff7fh uartauxstat r - 8 -- address name access block number of bits comment elm near equivalent register chaucer near equivalent register
1997 aug 01 100 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 ff80h adata rw - 8 see table 56 adata - ff81h ifctrl rw - 8 ifctrl - ff82h dbcl rw - 8 dbcl - ff83h dbch rw - 8 dbch - ff84h dtrg w - 8 dtrg - ff85h dtack w - 8 dtack - ff86h reset w - 8 reset - ff87h astat rw - 8 astat - ff88h itrg w - 8 itrg - ff89h adradr w - 8 adradr - ff8ah asamt rw - 8 asamt - ff8bh dtctr rw - 8 dtctr - ff8ch adrsel rw - 8 adrsel - ff8dh aintr rw - 8 aintr - ff8eh aerr rw - 8 aerr - ff8fh acmd r - 8 acmd - ff90h adctr r - 8 adctr - ff91h afeat r - 8 afeat - ff92h ifstat rw - 8 ifstat - ff93h apcmd r - 8 apcmd - ff94h hiconf0 rw - 8 -- ff95h hiconf1 rw - 8 -- ff96h hiseq rw - 8 -- ff97h shstat rw - 8 -- ff98h sherr rw - 8 -- ff99h hidev rw - 8 -- ff9ah histat r - 8 -- ff9bh 3 unused address locations ff9ch ff9dh address name access block number of bits comment elm near equivalent register chaucer near equivalent register
1997 aug 01 101 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 ff9eh multi_con -- 8 see table 100 -- ff9fh clk_con -- - clksel ffa0h transfercount (7 to 0) rw - 32 see table 56 -- ffa1h transfercount (15 to 8) rw --- ffa2h transfercount (23 to 16) rw --- ffa3h transfercount (31 to 24) rw --- ffa4h packetsize_store(l) rw - 16 -- ffa5h packetsize_store(h) rw --- ffa6h sequencer_status r - 8 -- ffa7h 25 unused address locations ffbfh ffc0h 32 generic addresses in 3-state locations ffdfh ffe0h 32 3-state address locations ffffh address name access block number of bits comment elm near equivalent register chaucer near equivalent register
1997 aug 01 102 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 13 application information fig.32 schematic diagram of SAA7391 in a typical application. handbook, full pagewidth mgk507 SAA7391 cache ram dac rom generic/ ncr controller microcontroller 8051 micro- controller disc servo cd-r encoder cd-dsp cd7 ace cd65 hd61 cd engine i 2 s-bus i 2 s-bus i 2 s-bus i 2 c-bus synch/s2b q-w (p, q) r-w iec 958 ide connector multiplexed address/data bus r/w psen ale int1, int2
1997 aug 01 103 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 14 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.50 22.15 21.85 0.69 0.59 1.40 1.10 7 0 o o 0.1 0.2 0.1 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 97-07-02 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 1.40 1.10 d 0 5 10 mm scale b p e q e a 1 a l p q detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
1997 aug 01 104 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 15 soldering 15.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 15.2 re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 15.3 wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1997 aug 01 105 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 16 definitions 17 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1997 aug 01 106 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 notes
1997 aug 01 107 philips semiconductors objective speci?cation atapi cd-r block encoder/decoder SAA7391 notes
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